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? 2012-2015 microchip technology inc. ds00001946a-page 1 highlights single chip hsic usb 2.0 to 10/100 ethernet controller integrated 10/100 etherne t mac with full-duplex support integrated 10/100 ethernet phy with hp auto- mdix support integrated usb 2.0 hi-speed device controller integrated hsic interface implements reduced power operating modes target applications embedded systems set-top boxes pvrs ce devices networked printers usb port replicators test instrumentation industrial key features usb device controller - fully compliant with hi-speed universal serial bus specification, revision 2.0 - supports hs (480 mbps) mode - four endpoints supported - supports vendor specific commands - integrated hsic interface - remote wakeup supported high-performance 10/100 ethernet controller - fully compliant with ieee 802.3/802.3u - integrated ethernet mac and phy - 10base-t and 100base-tx support - full- and half-duplex support - full- and half-duplex flow control - preamble generation and removal - automatic 32-bit crc generation and checking - automatic payload padding and pad removal - loop-back modes - tcp/udp/ip/icmp checksum offload support - flexible address filtering modes - one 48-bit perfect address - 64 hash-filtered multicast addresses - pass all multicast - promiscuous mode - inverse filtering - pass all incoming with status report - wakeup packet support - integrated ethernet phy - auto-negotiation - automatic polarity de tection and correction - hp auto-mdix support - link status change wake-up detection - support for three status leds - external mii and turbo mii support homepna ? and homeplug ? phy power and i/os - various low power modes - supports pci-like pme wake when usb host dis- abled -11 gpios - supports bus-powered and self-powered opera- tion - integrated power-on reset circuit - single external 3.3 v i/o supply - optional internal core regulator miscellaneous features - eeprom controller - supports custom o peration without eeprom - ieee 1149.1 (jtag) boundary scan - requires single 25 mhz crystal software - windows ? 8/7/xp/vista driver - linux ? driver - win ce driver -mac ? os driver - eeprom utility packaging - 56-pin vqfn (8 x 8 mm), rohs-compliant environmental - commercial temperature range (0c to +70c) - industrial temperature range (-40c to +85c) lan9730/lan9730i high-speed inter-chip (hsic) usb 2.0 to 10/100 ethernet controller downloaded from: http:///
lan9730/lan9730i ds00001946a-page 2 ? 2012-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicat ions to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documen tation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: microchips worldwide web site: http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 3 lan9730/lan9730i table of contents 1.0 introduction ..................................................................................................................................................................................... 5 2.0 pin description and configuration ................................................................................................................................................ 11 3.0 power connections ......................................................................................................... .............................................................. 27 4.0 functional description .................................................................................................... .............................................................. 29 5.0 pme operation ............................................................................................................. .............................................................. 115 6.0 register descriptions .................................................................................................................................................................. 119 7.0 operational charac teristics ............................................................................................... .......................................................... 195 8.0 packaging information ................................................................................................................................................................ 213 the microchip web site ........................................................................................................ ............................................................ 219 customer change notification service ............................................................................................................................................. 219 customer support ............................................................................................................................................................................. 219 product identification system ................................................................................................. .......................................................... 220 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 4 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 5 lan9730/lan9730i 1.0 introduction 1.1 general terms byte 8 bits csr control and status registers dword 32 bits fct fifo controller fifo first in first out buffer frame in the context of this document, a fram e refers to transfers on the ethernet interface. fsm finite state machine gpio general purpose i/o hsic high-speed inter-chip host external system (includes proce ssor, application software, etc.) level-triggered sticky bit this type of status bit is set wheneve r the condition that it represents is asserted. the bit remains set until the condition is no longer true and the sta- tus bit is cleared by writing a zero. lfsr linear feedback shift register mac media access controller mii media independent interface n/a not applicable packet in the context of this document, a packe t refers to transfers on the usb inter- face. por power on reset reserved refers to a reserved bit field or address. unless otherwise noted, reserved bits must always be zero for write operations. unless otherwise noted, values are not ensured when reading reserved bi ts. unless otherwise noted, do not read or write to reserved addresses. scsr system control and status register smi serial management interface tli transaction layer interface urx usb bulk-out packet receiver utx usb bulk-in packet transmitter word 16 bits zlp zero length usb packet downloaded from: http:///
lan9730/lan9730i ds00001946a-page 6 ? 2012-2015 microchip technology inc. 1.2 block diagram figure 1-1: block diagram figure 1-2: system diagram tap controller eeprom controller usb 2.0 device controller sram ethernet phy 10/100 ethernet mac fifo controller hsic interface lan9730/lan9730i mii: to optional external phy ethernet eeprom jtag hsic udc mac fct ram 7kx32 tli reg file 512x37 reg file 32x37 eeprom controller eth phy hsic i/f utx tap controller usb common block urx ctl m u x reg file 128x32 scsr cpm mii: to optional external phy downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 7 lan9730/lan9730i 1.2.1 overview the lan9730/lan9730i is a high performance solution for usb to 10/100 ethernet port bridging. with applications ranging from embedded systems, set-top boxes, and pvrs, to u sb port replicators, and test instrumentation, the device is targeted as a high-performance, low- cost usb/ethernet connectivity solution. the lan9730/lan9730i contains an inte grated 10/100 ethernet phy, hsic inte rface, hi-speed usb 2.0 device con- troller, 10/100 ethernet mac, tap controller, eeprom controller , and a fifo controller with a total of 30 kb of internal packet buffering. two kb of buffer memory are allocated to the transaction layer interface (tli), while 28 kb are allo- cated to the fifo controller (fct). the internal usb 2.0 device controller is compliant with the usb 2.0 hi-speed standard. the hsic interface is compliant with the high-speed interchip usb electrical specification revi sion 1.0. high-speed inter-chip (hsic) is a digital inter- connect bus that enables the use of usb technology as a low-power chip-to-chip interconnect at speeds up to 480 mb/ s. the device implements control, interr upt, bulk-in and bulk-out usb endpoints. the ethernet controller supports auto-negotiation, auto-polarity correction, hp auto-mdix, and is compliant with the ieee 802.3 and 802.3u standards. an external mii interface pr ovides support for an external fast ethernet phy, home- pna, and homeplug functionality. multiple power management features are provided, including various low-power modes, and magic packet, wake on lan and link status change wake events. these wake ev ents can be programmed to initiate a usb remote wakeup. a pci-like pme wake is also supported when the host controller is disabled. an internal eeprom controller exists to load various usb configuration informa tion and the device mac address. the integrated ieee 1149.1 comp liant tap controller provides boundary scan via jtag. 1.2.2 usb the usb portion of the lan9730/lan9730i consists of the usb device controller (udc), usb bulk-out packet receiver (urx), usb bulk-in packet tr ansmitter (utx), control block (ctl), system control and status registers (scsr), and hsic interface. the usb device controller (udc) contains a usb low-level pr otocol interpreter which impl ements the usb bus protocol, packet generation/extraction, pid/device id parsing, and crc coding/decoding with autonomous error handling. it has autonomous protocol handling functions such as stall condition clearing on setup packe ts, suspend/resume/reset con- ditions, and remote wakeup. it also autonomously handles cont ingency operations for error conditions such as retry for crc errors, data toggle errors, and generation of nyet, stall, ack, and nack depending on the endpoint buffer status. the udc implements four usb endpoints: control, interrupt, bulk-in, and bulk-out. the control block (ctl) manages traffic to/from the control en dpoint that is not handled by the udc and constructs the packets used by the interrupt endpoint. the ctl is responsible for handling some usb standard commands and all vendor specific commands. the vendor specific commands allow for efficient statistics collection and access to the scsr. the urx and utx implement the bulk-out and bulk-in pipes, respectively, which connect the usb host and the udc. they perform the following functions: the urx passes usb bulk-out packets to the fifo controll er (fct). it tracks whether or not a usb packet is errone- ous. it instructs the fct to flush erroneous packets by rewinding its write pointer. the utx retrieves ethernet frames from the fct and constr ucts usb bulk-in packets from them. if the handshake for a transmitted bulk-in packet does not complete, the utx is capable of retransmitting the packet. the utx will not instruct the fct to advance its read head pointer until the current usb packet has been succ essfully transmitted to the usb host. both the urx and utx are responsible for handling ethernet frames encapsulated over usb by one of the following methods: multiple ethernet frames per usb bulk packet single ethernet frame per usb bulk packet the udc also implements the system contro l and status register (scsr) space used by the host to obtain status and control overall system operation. the integrated hsic interface is compliant with the high-speed interchip usb elec trical specification revision 1.0 (09- 23-07) and supports the hi- speed mode of operation. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 8 ? 2012-2015 microchip technology inc. 1.2.3 fifo controller (fct) the fifo controller uses a 28 kb internal sram to buffer rx and tx traffic. 20 kb are allocated for received ethernet- usb traffic (rx buffer), while 8 kb are allocated for usb-ethe rnet traffic (tx buffer). bu lk-out packets from the usb controller are directly stored into the tx buffer. the fct is responsible for extracting ethernet frames from the usb packet data and passing the frames to the mac. ethernet frames are directly stor ed into the rx buffer and become the basis for bulk-in packets. the fct pass es the stored data to the utx in blocks typically 512 bytes in size. 1.2.4 ethernet lan9730/lan9730i integrates an ieee 802.3 phy for twisted pa ir ethernet applications and a 10/100 ethernet media access controller (mac). the phy can be configured for either 100 mbps (100base-tx) or 10 mbps (10 base-t) ethernet operation in either full- or half-duplex configurations. the phy block includes auto-negotiation, auto-polarity correction, and auto-mdix. minimal external components are required for the utilization of the integrated phy. optionally, an external phy may be used via the mii (media independent interface) port, ef fectively bypassing the inter- nal phy. this option allows support for homepna and homeplug applications. the transmit and receive data paths within the 10/100 ether net mac are independent, allo wing for the highest perfor- mance possible, particularly in full-duplex mode. the et hernet mac operates in store and forward mode, utilizing an independent 2 kb buffer for transmitted frames, and a smalle r 128 byte buffer for received frames. the ethernet mac data paths connect to the fifo controller. the mac also implements a control and status register (csr) space used by the host to obtain status and control its operation. the ethernet mac/phy supports numerous power managem ent wakeup features, including magic packet, wake on lan, and link status change. eight wakeup frame filters are provided by the device. 1.2.5 power management the lan9730/lan9730i features fo ur variations of usb suspend: suspend0, suspend1, suspend2, and sus- pend3. these modes allow the applicatio n to select the ideal balance of remo te wakeup functionality and power con- sumption. suspend0: supports gpio, wake on lan and magic packet events. this state reduces power by stopping the clocks of the mac and other internal modules. suspend1: supports gpio and link status change for remo te wakeup events. this suspend state consumes less power than suspend0. suspend2: supports only gpio assertion for a remote wakeup event. this is the default suspend mode for the device. suspend3: supports gpio and good packet events. a good packet is a received frame passing certain filtering constraints independent of those im posed on wake on lan and magic packet frames. this suspend state con- sumes power at a level similar to the full operational state, however, it allows for power savings in the host cpu. refer to section 4.12, "wake events" for more information on the usb suspend states and the wake events supported in each state. 1.2.6 eeprom cont roller (epc) lan9730/lan9730i contains an eeprom controller for connec tion to an external eeprom. this allows for the auto- matic loading of static configuration data upon power on reset, pin reset or software reset. the eeprom can be con- figured to load usb descriptors, usb device configuration, and mac address. 1.2.7 general purpose i/o when configured for internal phy mode, up to eleven gp ios are supported. all gpios can serve as remote wakeup events when the lan9730/lan9730i is suspended. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 9 lan9730/lan9730i 1.2.8 tap controller ieee 1149.1 compliant tap controller suppor ts boundary scan and various test modes. the device includes an integrated jtag boundary-scan test port for board-level testing. the interface consists of five pins (tdo, tdi, tck, tms, and ntrst) and includes a state machine, data register array and an instruction register. the jtag pins are described in table 2-3, jtag pins . the jtag interface conforms to the ieee standard 1149.1 - 1990 standard test access port (tap) and boundary-scan architecture . all input and output data is synchronous to the tck test clock input. tap input signals tms and tdi are clocked into the test logic on the rising edge of tck, while the output signal tdo is clocked on the falling edge. the jtag logic is reset via power on reset (por) or when the ntrst pin is asserted active-low. the implemented ieee 1149.1 instructions and their op codes are shown in ta b l e 1 - 1 . 1.2.9 control and status registers (csr) lan9730/lan9730is functions are controlle d and monitored by the host via the control and status registers (csrs). this register space includes registers that control and monitor the usb controller, as well as elements of overall system operation (system control and status registers - scsrs), t he mac (mac control and status registers - mcsrs), and the phy (accessed indirectly through the mac via the mii_access and mii_data registers). the csr may be accessed via the usb vendor commands (register read/register write). refer to section 4.3.3, "usb ven- dor commands" for more information. 1.2.10 resets lan9730/lan9730i supports the following system reset events: power on reset (por) hardware reset input pin reset (nreset) lite reset (lrst) (does not affect the udc) software reset (srst) usb reset the device supports the following module level reset events: ethernet phy softwa re reset (phy_rst) ntrst pin reset for tap controller 1.2.11 test features read/write access to inte rnal srams is provided via the csrs. jtag-bas ed usb bist is available. full internal scan and at speed scan are supported. table 1-1: ieee 1149.1 op codes instruction op code comment bypass 111111b mandatory instruction sample/preload 000100b mandatory instruction extest 000001b mandatory instruction highz 000011b optional instruction idcode 001010b optional instruction note: the jtag device id is 00091445h. note: all digital i/o pins support ieee 1149.1 operation. an alog pins and the xi/xo pins do not support ieee 1149.1 operation. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 10 ? 2012-2015 microchip technology inc. 1.2.12 system software lan9730/lan9730i software drivers are ava ilable for the following operating systems: windows 8 windows 7 windows vista windows xp linux win ce mac os in addition, an eeprom programmi ng utility is avail able for confi guring the external eeprom. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 11 lan9730/lan9730i 2.0 pin description and configuration note: ** this pin provides additional pme related functionality. refer to the respective pin descriptions and chapter 5.0, "pme operation" for additional information. note: *** gpio7 may provide additional phy link up related functionality. refer to section 4.12.2.4, "enabling external phy link up wake events" for additional information. note: when hp auto-mdix is activated, the txn/txp pins can function as rxn/rxp and vice-versa. note: exposed pad (vss) on bottom of pa ckage must be connected to ground. figure 2-1: pin assignments (top view) vss lan9730 56-pin vqfn (top view) txen rxdv nspd_led/gpio10 ** txer 12 3 4 5 6 7 8 9 1011 12 13 14 1516 17 18 19 20 21 22 23 24 25 26 27 28 4241 40 39 38 37 36 35 34 33 32 31 30 29 5655 54 53 52 51 50 49 48 47 46 45 44 43 test2 vdd12a hsic_strobe hsic_data vdd12pll vdd33a exres rxp rxn vdd33a txp txn nphy_int rxclk tdi/rxd3 tms/rxd2 tck/rxd1 tdo/nphy_rst ntrst/rxd0 vdd33io phy_sel test1 eedi eedo/automdix_en eecs eeclk rxer crs/gpio3 col/gpio0 ** txclk vdd33io core_reg_en vdd12core vdd33io vdd33io txd3/gpio7/50driver_en *** txd2/gpio6/port_swap txd1/gpio5/rmt_wkp txd0/gpio4/eep_disable nlnka_led/gpio9 ** nfdx_led/gpio8 ** vdd33io nreset ** mdio/gpio1 ** mdc/gpio2 vdd12core slew_tune xo xi vdd12usbpll usbrbias vdd33a downloaded from: http:///
lan9730/lan9730i ds00001946a-page 12 ? 2012-2015 microchip technology inc. table 2-1: mii interface pins num pins name symbol buffer type description 1 receive error (internal phy mode) rxer is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. receive error (external phy mode) rxer is (pd) in external phy mode, the signal on this pin is input from the external phy and indicates a receive error in the packet. 1 transmit error (internal phy mode) txer is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit error (external phy mode) txer o8 (pd) in external phy mode, this pin functions as an output to the external phy and indicates a trans- mit error. 1 transmit enable (internal phy mode) txen is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit enable (external phy mode) txen o8 (pd) in external phy mode, this pin functions as an output to the external phy and indicates valid data on txd[3:0]. 1 receive data valid (internal phy mode) rxdv is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. receive data valid (external phy mode) rxdv is (pd) in external phy mode, the signal on this pin is input from the external phy and indicates valid data on rxd[3:0]. 1 receive clock (internal phy mode) rxclk is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. receive clock (external phy mode) rxclk is (pd) in external phy mode, this pin is the receiver clock input from the external phy. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 13 lan9730/lan9730i 1 transmit clock (internal phy mode) txclk is/o8 (pu) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit clock (external phy mode) txclk is (pu) in external phy mode, this pin is the transmitter clock input from the external phy. 1 carrier sense (internal phy mode) crs is/o8 (pu) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. carrier sense (external phy mode) crs is (pd) in external phy mode, the signal on this pin is input from the external phy and indicates a net- work carrier. general pur- pose i/o 3 (internal phy mode only) gpio3 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. 1 mii collision detect (internal phy mode) col is/o8 (pu) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. mii collision detect (external phy mode) col is (pd) in external phy mode, the signal on this pin is input from the external phy and indicates a colli- sion event. general pur- pose i/o 0 (internal phy mode only) gpio0 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. note: this pin may be used to signal pme when internal phy and pme modes of operation are in effect. refer to chapter 5.0, "pme operation" for additional information. table 2-1: mii interface pins (continued) num pins name symbol buffer type description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 14 ? 2012-2015 microchip technology inc. 1 management data (internal phy mode) mdio is/o8 (pu) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. management data (external phy mode) mdio is/o8 (pd) in external phy mode, this pin provides the man- agement data to/from the external phy. general pur- pose i/o 1 (internal phy mode only) gpio1 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. note: this pin may serve as the pme_mode_sel input when internal phy and pme modes of operation are in effect. refer to chapter 5.0, "pme operation" for additional information. 1 management clock (internal phy mode) mdc is/o8 (pu) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. management clock (external phy mode) mdc o8 (pd) in external phy mode, this pin outputs the man- agement clock to the external phy. general pur- pose i/o 2 (internal phy mode only) gpio2 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. table 2-1: mii interface pins (continued) num pins name symbol buffer type description downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 15 lan9730/lan9730i 1t r a n s m i t d a t a 3 (internal phy mode) txd3 is/o8 (pu) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit data 3 (external phy mode) txd3 o8 (pu) in external phy mode, this pin functions as the transmit data 3 output to the external phy. general pur- pose i/o 7 (internal phy mode only) gpio7 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. note: gpio7 may provide additional external phy link up related functionality. refer to section 4.12.2.4, "enabling external phy link up wake events" for additional information. hsic output impedance configuration strap 50driver_en is (pu) the 50driver_en strap selects the driver out- put impedance for the hsic_data and hsic_strobe pins. 0 = 40 ? output impedance 1 = 50 ? output impedance see note 2-1 for more information on configura- tion straps. table 2-1: mii interface pins (continued) num pins name symbol buffer type description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 16 ? 2012-2015 microchip technology inc. 1t r a n s m i t d a t a 2 (internal phy mode) txd2 is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit data 2 (external phy mode) txd2 o8 (pd) in external phy mode, this pin functions as the transmit data 2 output to the external phy. general pur- pose i/o 6 (internal phy mode only) gpio6 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output, or a schmitt-triggered input. hsic port swap config- uration strap port_swap is (pd) swaps the mapping of hsic_data and hsic_strobe. 0 = the hsic_data and hsic_strobe pin functionality is not swapped. 1 = the hsic_data and hsic_strobe pin functionality is swapped. see note 2-1 for more information on configura- tion straps. 1t r a n s m i t d a t a 1 (internal phy mode) txd1 is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit data 1 (external phy mode) txd1 o8 (pd) in external phy mode, this pin functions as the transmit data 1 output to the external phy. general pur- pose i/o 5 (internal phy mode only) gpio5 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. remote wakeup con- figuration strap rmt_wkp is (pd) this strap configures the default descriptor values to support remote wakeup. this strap is overrid- den by the eeprom. 0 = remote wakeup is not supported. 1 = remote wakeup is supported. see note 2-1 for more information on configura- tion straps. table 2-1: mii interface pins (continued) num pins name symbol buffer type description downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 17 lan9730/lan9730i 1t r a n s m i t d a t a 0 (internal phy mode) txd0 is/o8 (pd) in internal phy mode, this pin can be configured to display the respective internal mii signal. refer to the internal mii visibility enable (ime) bit of the hardware configuration register (hw_cfg) on page 125 for additional information. transmit data 0 (external phy mode) txd0 o8 (pd) in external phy mode, this pin functions as the transmit data 0 output to the external phy. general pur- pose i/o 4 (internal phy mode only) gpio4 is/o8/ od8(pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. eeprom disable con- figuration strap eep_disable is (pd) this strap disables the autoloading of the eeprom contents. the assertion of this strap does not prevent register access to the eeprom. 0 = eeprom is recognized if present. 1 = eeprom is not recognized even if it is pres- ent. see note 2-1 for more information on configura- tion straps. table 2-1: mii interface pins (continued) num pins name symbol buffer type description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 18 ? 2012-2015 microchip technology inc. note 2-1 configuration strap values are latched on power on reset (por) or external chip reset (nreset) . configuration straps are identified by an underlined sym bol name. pins that func tion as configuration straps must be augmented with an external resistor when connected to a load. refer to section 4.14, "configuration straps" for additional information. table 2-2: eeprom pins num pins name symbol buffer type description 1 eeprom data in eedi is (pd) this pin is driven by the eedo output of the external eeprom. 1 eeprom data out eedo o8 (pu) this pin drives the eedi input of the external eeprom. auto-mdix enable con- figuration strap automdix_en is (pu) determines the default auto-mdix setting. 0 = auto-mdix is disabled. 1 = auto-mdix is enabled. see note 2-1 for more information on configura- tion straps. 1 eeprom chip select eecs o8 this pin drives the chip select output of the exter- nal eeprom. note: the eecs output may tri-state briefly during power-up. some eeprom devices may be prone to false selection during this time. when an eeprom is used, an external pull-down resistor is recommended on this signal to prevent false selection. refer to your eeprom manufacturers datasheet for additional information. 1 eeprom clock eeclk o8 (pd) this pin drives the eeprom clock of the external eeprom. note: this pin must be pulled-up externally for proper operation. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 19 lan9730/lan9730i table 2-3: jtag pins num pins name symbol buffer type description 1j t a g t e s t port reset (internal phy mode) ntrst is (pu) in internal phy mode, this active-low pin func- tions as the jtag test port reset input. receive data 0 (external phy mode) rxd0 is (pd) in external phy mode, this pin functions as the receive data 0 input from the external phy. 1j t a g t e s t data out (internal phy mode) tdo o8 in internal phy mode, this pin functions as the jtag data output. phy reset (external phy mode) nphy_rst o8 in external phy mode, this active-low pin func- tions as the phy reset output. 1j t a g t e s t clock (internal phy mode) tck is (pu) in internal phy mode, this pin functions as the jtag test clock. the maximum operating fre- quency of this clock is 25 mhz. receive data 1 (external phy mode) rxd1 is (pd) in external phy mode, this pin functions as the receive data 1 input from the external phy. 1j t a g t e s t mode select (internal phy mode) tms is (pu) in internal phy mode, this pin functions as the jtag test mode select. receive data 2 (external phy mode) rxd2 is (pd) in external phy mode, this pin functions as the receive data 2 input from the external phy. 1j t a g t e s t data input (internal phy mode) tdi is (pu) in internal phy mode, this pin functions as the jtag data input. receive data 3 (external phy mode) rxd3 is (pd) in external phy mode, this pin functions as the receive data 3 input from the external phy. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 20 ? 2012-2015 microchip technology inc. table 2-4: miscellaneous pins num pins name symbol buffer type description 1 phy select phy_sel is (pd) selects whether to use the internal ethernet phy or the external phy connected to the mii port. 0 = internal phy is used. 1 = external phy is used. note: when in external phy mode, the internal phy is placed into general power down after a por. refer to section 4.6, "10/100 internal ethernet phy" for details. 1 system reset nreset is (pu) this active-low pin allows external hardware to reset the device. note: this pin may be used to signal pme_clear when pme mode of operation is in effect. refer to chapter 5.0, "pme operation" for additional information. 1 ethernet full-duplex indicator led nfdx_led od12 (pu) this pin is driven low (led on) when the ethernet link is operating in full-duplex mode. general pur- pose i/o 8 gpio8 is/o12/ od12 (pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. note: this pin may be used to signal pme when external phy and pme modes of operation are in effect. refer to chapter 5.0, "pme operation" for additional information. note: by default this pin is configured as a gpio. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 21 lan9730/lan9730i 1 ethernet link activity indi- cator led nlnka_led od12 (pu) this pin is driven low (led on) when a valid link is detected. this pin is pulsed high (led off) for 80 ms whenever transmit or receive activity is detected. this pin is then driven low again for a minimum of 80 ms, after which time it will repeat the process if tx or rx activity is detected. effec- tively, led2 is activate d solid for a link. when transmit or receive activity is sensed, led2 will function as an activity indicator. general pur- pose i/o 9 gpio9 is/o12/ od12 (pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. note: this pin may serve as the pme_mode_sel input when external phy and pme modes of operation are in effect. refer to chapter 5.0, "pme operation" for additional information. note: by default this pin is configured as a gpio. 1 ethernet speed indica- tor led nspd_led od12 (pu) this pin is driven low (led on) when the ethernet operating speed is 100 mbs, or during auto-nego- tiation. this pin is driven high during 10 mbs oper- ation or during line isolation. general pur- pose i/o 10 gpio10 is/o12/ od12 (pu) this general purpose i/o pin is fully programma- ble as either a push-pull output, an open-drain output or a schmitt-triggered input. note: this pin may serve as a wakeup pin whose detection mode is selectable when external phy and pme modes of operation are in effect. refer to chapter 5.0, "pme operation" for additional information. note: by default this pin is configured as a gpio. 1 core regula- tor enable core_reg_en ai this pin enables/disables the internal core logic voltage regulator. when tied low to vss, the internal core regulator is disabled and +1.2 v must be supplied to the device by an external source. when tied high to +3.3 v, the internal core regula- tor is enabled. refer to chapter 3.0, "power connections" and the device reference schematics for connection information. 1 test 1 test1 - this pin must always be connected to vss for proper operation. table 2-4: miscellaneous pins (continued) num pins name symbol buffer type description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 22 ? 2012-2015 microchip technology inc. 1 test 2 test2 - this pin must always be connected to +3.3 v for proper operation. 1 crystal input xi iclk external 25 mhz crystal input. note: this pin can also be driven by a single- ended clock oscillator. when this method is used, xo should be left unconnected. 1 crystal out- put xo oclk external 25 mhz crystal output. table 2-4: miscellaneous pins (continued) num pins name symbol buffer type description downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 23 lan9730/lan9730i table 2-5: usb pins num pins name symbol buffer type description 1 hsic data hsic_data hsic bi-directional double data rate (ddr) data sig- nal that is synchronou s to the hsic_strobe signal as defined in the high-speed inter-chip usb electrical specification, version 1.0 . 1 hsic strobe hsic_strobe hsic bi-directional data strobe signal as defined in the high-speed inter-chip usb electrical specifica- tion, version 1.0 . 1 hsic slew tune slew_tune is (pd) applies a 30% slew rate boost to the hsic_data and hsic_strobe pins when driven high. 1 external usb bias resistor usbrbias ai used for setting hs transmit current level and on- chip termination impedance. connect to an exter- nal 12.0 k ? 1.0% resistor to ground. table 2-6: ethernet phy pins num pins name symbol buffer type description 1 ethernet tx data out negative txn aio the transmit data outputs may be swapped inter- nally with receive data inputs when auto-mdix is enabled. 1 ethernet tx data out positive txp aio the transmit data outputs may be swapped inter- nally with receive data inputs when auto-mdix is enabled. 1 ethernet rx data in nega- tive rxn aio the receive data inputs may be swapped inter- nally with transmit data outputs when auto-mdix is enabled. 1 ethernet rx data in posi- tive rxp aio the receive data inputs may be swapped inter- nally with transmit data outputs when auto-mdix is enabled. 1 phy inter- rupt (internal phy mode) nphy_int o8 in internal phy mode, this pin can be configured to output the internal phy interrupt signal. note: the internal phy interrupt signal is active-high. phy interrupt (external phy mode) nphy_int is (pu) in external phy mode, the active-low signal on this pin is input from the external phy and indi- cates a phy interru pt has occurred. 1 external phy bias resistor exres ai used for the internal bias circuits. connect to an external 12.0 k ? 1.0% resistor to ground. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 24 ? 2012-2015 microchip technology inc. table 2-7: power pins and ground pad num pins name symbol buffer type description 5 +3.3 v i/o power vdd33io p refer to chapter 3.0, "power connections" and the device reference schematics for connection information. 3 +3.3 v ana- log power vdd33a p refer to chapter 3.0, "power connections" and the device reference schematics for connection information. 2 +1.2 v digital core power vdd12core p refer to chapter 3.0, "power connections" and the device reference schematics for connection information. 1 +1.2 v usb pll power vdd12usbpll p this pin must be connected to vdd12core for proper operation. refer to chapter 3.0, "power connections" and the device reference schematics for additional connection information. 1 +1.2 v hsic power vdd12a p this pin must be connected to vdd12core for proper operation. refer to chapter 3.0, "power connections" and the device reference schematics for connection information. 1 +1.2 v ether- net pll power vdd12pll p this pin must be connected to vdd12core for proper operation. refer to chapter 3.0, "power connections" and the device reference schematics for additional connection information. exposed pad on package bottom ( figure 2-1 ) ground vss p common ground downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 25 lan9730/lan9730i 2.1 pin assignments note 2-2 this pin provides additional pme-related functionalit y. refer to the respective pin descriptions and chapter 5.0, "pme operation" for additional information. table 2-8: 56-vqfn package pin assignments pin num pin name pin num pin name pin num pin name pin num pin name 1 nphy_int 15 vdd33a 29 eeclk 43 txen 2 txn 16 usbrbias 30 eecs 44 rxer 3 txp 17 vdd12usbpll 31 eedo/ automdix_en 45 crs/gpio3 4 vdd33a 18 xi 32 eedi 46 col/gpio0 note 2-2 5 rxn 19 xo 33 test1 47 txclk 6 rxp 20 slew_tune 34 phy_sel 48 vdd33io 7 exres 21 vdd12core 35 vdd33io 49 core_reg_en 8 vdd33a 22 mdc/gpio2 36 ntrst/rxd0 50 vdd12core 9 vdd12pll 23 mdio/gpio1 note 2-2 37 tdo/nphy_rst 51 vdd33io 10 hsic_data 24 nreset note 2-2 38 tck/rxd1 52 vdd33io 11 hsic_strobe 25 vdd33io 39 tms/rxd2 53 txd3/gpio7/ 50driver_en 12 vdd12a 26 nfdx_led/ gpio8 40 tdi/rxd3 54 txd2/gpio6/ port_swap 13 test2 27 nlnka_led/ gpio9 note 2-2 41 rxclk 55 txd1/gpio5/ rmt_wkp 14 txer 28 nspd_led/ gpio10 note 2-2 42 rxdv 56 txd0/gpio4/ eep_disable exposed pad must be connected to vss downloaded from: http:///
lan9730/lan9730i ds00001946a-page 26 ? 2012-2015 microchip technology inc. 2.2 buffer types table 2-9: buffer types buffer type description is schmitt-triggered input o8 output with 8 ma sink and 8 ma source od8 open-drain output with 8 ma sink o12 output with 12 ma sink and 12 ma source od12 open-drain output with 12 ma sink hsic high-speed inter-chip (hsic) usb elec trical specification, version 1.0 compliant input/out- put pu 50 a (typical) internal pull-up. unless other wise noted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. pd 50 a (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals ex ternal to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 27 lan9730/lan9730i 3.0 power connections the lan9730/lan9730i can be operated with the inte rnal core regulator enabled or disabled. figure 3-1 illustrates the power connections for operating the devic e with the internal regulator enabled. figure 3-2 illustrates the power connec- tions for operating the device with the inte rnal regulator disabled. in this mode, +1.2 v must be supplied to the device by an external source. figure 3-1: power connections - internal regulator enabled +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enabled vdd33io +3.3 v vdd12core vdd12core core logic 50 21 vdd12usbpll 17 0.1 f 51 vdd33a 4 52 vdd33io 0.1 f 25 vdd33io vdd33io 48 35 vdd33io 0.1 f 0.1 f 0.1 f0.1 f 0.1 f lan9730/lan9730i vdd33a 8 vdd33a 15 0.1 f 56-pin vqfn 0.5 a 120 ohm @ 100 mhz core_reg_en vdd12pll 9 0.1 f pll & ethernet phy 0.5 a 120 ohm @ 100 mhz 0.1 f 0.5 a 120 ohm @ 100 mhz 12 vss exposed pad hsic usb phy vdd12a 0.1 f 49 0.5 a 120 ohm @ 100 mhz +3.3 v 0.1 f 0.1 f 1 f downloaded from: http:///
lan9730/lan9730i ds00001946a-page 28 ? 2012-2015 microchip technology inc. figure 3-2: power connections - internal regulator disabled +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator disabled vdd33io +3.3 v vdd12core vdd12core core logic 50 21 vdd12usbpll 17 0.1 f 51 vdd33a 4 52 vdd33io 0.1 f 25 vdd33io vdd33io 48 35 vdd33io 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f lan9730/lan9730i vdd33a 8 vdd33a 15 0.1 f 56-pin vqfn 0.5 a 120 ohm @ 100 mhz core_reg_en vdd12pll 9 0.1 f pll & ethernet phy 0.5 a 120 ohm @ 100 mhz 0.1 f 0.5 a 120 ohm @ 100 mhz 12 vss exposed pad hsic usb phy vdd12a 0.1 f 49 +1.2 v 0.5 a 120 ohm @ 100 mhz 0.1 f 0.1 f 1 f downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 29 lan9730/lan9730i 4.0 functional description 4.1 functional overview the lan9730/lan9730i usb 2.0 to 10/1 00 ethernet controller consists of the following major functional blocks: hsic interface usb 2.0 device controller (udc) fifo controller (fct) and associated sram 10/100 ethernet mac 10/100 internal ethernet phy ieee 1149.1 tap controller eeprom controller (epc) the following sections discuss the features of each block. a block diagram of the device is shown in figure 1-1 . 4.2 hsic interface the hsic interface is compliant with the high-speed interchi p usb electrical specification revision 1.0. high-speed inter-chip (hsic) is a digital interconnect bus that enables the use of usb technology as a low-power chip-to-chip inter- connect at speeds up to 480 mb/s. 4.3 usb 2.0 device controller (udc) the usb functionality in the device consists of five major parts. the hsic interface (discussed in section 4.2 ), ucb (usb common block), udc (usb device controller), urx (usb bulk-out receiver), utx (usb bulk-in receiver), and ctl (usb control block). they are represented as the hsic interface and udc, collectively, in figure 1-1 . the ucb generates various clocks, including the system clocks of the device. the urx and utx implement the bulk- out and bulk-in endpoints respectively. the ctl manages control and interrupt endpoints. the udc is a usb low-level protocol interpreter. the udc controls the usb bus protocol, packet gen eration/extraction, pid/device id parsing, and crc coding/decoding with autonom ous error handling. it is capable of operating either in usb 1.1 or 2.0 compliant modes. it ha s autonomous protocol handling functions such as stall condition clearing on setup packets, suspend/resume/reset conditions, and remote wakeup. it also autonomously handles error conditions such as retry for crc errors, data toggle errors, and generation of nyet, stall, ack and nack, depending on the endpoint buffer status. the udc is configured to support one configuration, one interface, one al ternate setting, and four endpoints. 4.3.1 supported endpoints table 4-1 lists the supported endpoints. the following subsections discuss these endpoints in detail. the urx and utx implement the bulk-out and bulk-in endpoints, respectively. the ctl manages the control and interrupt endpoints. table 4-1: supported endpoints endpoint number description 0 control endpoint 1 bulk-in endpoint 2 bulk-out endpoint 3 interrupt endpoint downloaded from: http:///
lan9730/lan9730i ds00001946a-page 30 ? 2012-2015 microchip technology inc. 4.3.1.1 endpoint 1 (bulk-in) the bulk-in endpoint is controlled by the utx (usb bulk-i n transmitter). the utx is responsible for encapsulating ethernet data into a usb bulk-in packet. ethernet frames are retrieved from the fcts rx fifo. the utx supports the following two modes of operation: mef and sef, selected via the multiple ethernet frames per usb packet (mef) bit of the hardware configuration register (hw_cfg) . mef: multiple ethernet frames per bulk-in packet. this mode will maximize usb bus utilization by allowing multi- ple ethernet frames to be packed into a usb packet. frames greater than 512 bytes are split across multiple bulk- in packets. sef: single ethernet frame per bulk-in packet. this mode will not maximize usb bus utilization, but can poten- tially ease the burden on a low end host processor. fram es greater than 512 bytes are split across multiple bulk- in packets. each ethernet frame is prepended with an rx status word by the fct. the status word co ntains the frame length that is used by the utx to perform the encapsulation functions. the rx status word is generated by the rx transaction layer interface (rx tli). the tli resides between the mac and the fct. padding may be inserted between the rx status word and t he ethernet frame by the fct. this condition exists when the rxdoff register has a nonzero value (refer to hardware configuration register (hw_cfg) for details). the pad- ding is implemented by the fct barrel shifting the ethernet frame by th e specified byte offset. in accordance with the usb protocol, the utx terminates a burst with either a zlp or a bulk-in packet with a size of less than the bulk-in maximum packet size (512 bytes). the zlp is needed when the total amount of data transmitted is a multiple of a bulk-in packet size. the utx monitors the rx fifo size signal from the fct to determine when a burst has ended. an ethernet frame always begins on a dword boundary. in mef mode, the utx will not concatenate the end of the current frame and the beginning of the next frame into t he same dword. therefore, th e last dword of an ethernet frame may have unused bytes added to ensure dword alignmen t of the next frame. the addition of pad bytes depends on whether another frame is available for transmission after the current one. if the current fr ame is the last frame to be transmitted, no pad bytes will be added, as the usb protocol allows for termination of the packet on a byte boundary. if, however, another frame is available for transmission, the current frame will be padded out so that it ends on the dword boundary. this ensures the next frame to be transmitted will start on a dword boundary. if the utx receives a bulk-in token when the rx fifo is empty, it will transmit a zlp. figure 4-1: mef usb encapsulation note: in sef mode, a zlp is transmitted if the ethernet frame is the same size as a bulk-in packet, or a multiple of the bulk-in packet size. note: any unused bytes that were added to the last dword of a frame are not counted in the length field of the rx status word. note: the host ignores unused bytes that exist in the fi rst dword and last words of an ethernet frame. rx status word ethernet frame 512 byte usb bulk frame ethernet frame rx status word rx status word ethernet frame rx status word ethernet frame rx status word ethernet frame rx status word ethernet frame 512 byte usb bulk frame 512 byte usb bulk frame 512 byte usb bulk frame downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 31 lan9730/lan9730i once a decision is made to end a transfer and a short packet or zlp has been sent, it is po ssible that an ethernet frame will arrive prior to the utx seeing an ack from the host fo r the previous bulk-in packet. in this case, the utx must continue to repeat the short packet or zl p until the ack is received for the end of the previous transfer. the utx must not start a new transfer, or re-use the previous data toggle, to begin sending the next ethernet frame until the ack has been received for the end of the previous transfer. in order to more efficiently utilize usb bandwidth in mef mode, the utx has a mechanism for delaying the transmission of a short packet, or zlp. this mode entail s having the utx wait a time defined by the bulk-in delay register (bulk_in_dly) before terminating the burst. a value of zero in this register disables this feature. by default, a delay of 34 s is used. after the utx transmits the last usb wpacketsize packet in a burst, the utx will enable an internal timer. when the bulk-in delay time expires, any bulk-in data will be transmitted upon reception of the next bulk-in token. if enough data arrives before the timer elapses to build at least one maximum sized packet, then the utx will transmit this packet when it receives the next bulk-in token. after packet transmission, the utx will then reset its internal timer and delay the short packet, or zlp, transmission until the bulk-in delay time elapses. in the case where the fifo is empty and a single ether net packet less than the usb wpacketsize has been received, the utx will enable its internal timer. if enough data arrives before the timer elapses to build at least one maximum sized packet, then the utx will transmit this packet when it receives the next bulk-in token and will reset the internal timer. otherwise, the short packet, or zlp, is sent in response to the first bulk-in token received after the timer expires. the utx will nack any bulk-in tokens while waiting for the bulk-in delay to elapse. this nack response is not affected by the bulk-in empty response (bir) . the bulk-in empty response (bir) setting only applies after the bulk-in delay time expires. the utx, via the burst cap register (burst_cap) , is capable or prematurely term inating a burst. when the amount transmitted exceeds the value specified in this register, the utx transmits a zlp after the current bulk-in packet com- pletes. the burst cap register (burst_cap) uses units of usb packet size (512 bytes). to enable use of the burst cap register, the burst cap enable (bce) bit in the hardware configuration register (hw_cfg) must be set. for proper operation, the burst_cap field should be set to a value greater than 4. burst cap enforcement is disabled if burst_- cap is set to a value less than or equal to 4. whenever burst cap enforcement is disabled, the utx will respond with a zlp (when bulk-in empty response (bir) =0) or with nack (when bulk-in empty response (bir) = 1). whenever burst cap enforcement is enabled ( burst_cap value is legal), the following holds: let burst = burst_cap * 512 the burst may terminate at burst-4, burst-3, burst-2, burst-1, or b urst bytes, or, when the rx fifo runs out of data. the burst is terminated wi th either a short usb packet or with a zlp. in the case of an error condition, the utx will issue a re wind to the fct. this occurs when the utx completes trans- mitting a bulk-in packet and does not receive an ack from t he host. in this case, the next frame received by the utx will be another in token and the bulk-in packet is retransmitt ed. when the ack is finally received, the utx notifies the fct. the fct will then advance the read head pointer to the next packet. note: when using sef mode, there will never be any unused bytes added for end alignment padding. the usb transfer always ends on the last byte of the ethernet frame. note: when rx coe is enabled, the last byte would pertain to the rx coe word. note: ethernet frames are not fragmented across bursts when using burst cap enforcement. note: the utx will never stall the endpoint. the endpoint can only be stalled by the host. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 32 ? 2012-2015 microchip technology inc. figure 4-2: usb bulk-in transaction summary in token data in transfer ack zero length packet transfer stall data error in token error host function ack downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 33 lan9730/lan9730i 4.3.1.2 endpoint 2 (bulk-out) the bulk-out endpoint is controlled by the urx (usb bulk-out receiver). the urx is responsible for receiving ether- net data encapsulated over a usb bulk-out packet. unlike th e utx, the urx does not explic itly track ethernet frames. it views all received packets as purely usb data. the extracti on of ethernet frames is handl ed by the fct and the trans- action layer interface (tli). the urx always simultaneously supports multiple ethernet fr ames per usb packet, as well as a single ethernet frame per usb packet. no mechanism ex ists to select between modes. the urx monitors the amount of free sp ace in the tx fifo. if at least 512 by tes of space exists, the urx can accept an additional bulk-in frame and responds to a bulk-out token with an ack or n yet. the nyet response is used when less than 1024 bytes of free space exist. this means that the current bulk-out packet was accepted, but room does not exist for a second packet. if less than 512 bytes exist, the urx responds with a nack. the urx supports the ping protocol. in the case where the bulk-out packet is errored, the urx does not respond to the host. the urx will request that the fct rewinds the packet. it is the hosts responsib ility to retransmit the packet at a later time. the fct notifies the urx when it detects loss of sync. when this occurs, the urx stalls the bulk-out pipe. this is an appropriate response, as loss of sync is a catastr ophic error. this behavior is configurable via the stall bulk-out pipe disable (sbp) bit of the hardware configuration register (hw_cfg) on page 125 . figure 4-3: usb bulk-out transaction summary host function out token data out transfer ack nyet stall ping data error ack nak nak downloaded from: http:///
lan9730/lan9730i ds00001946a-page 34 ? 2012-2015 microchip technology inc. 4.3.1.3 endpoint 3 (interrupt) the interrupt endpoint is responsible for indicating device stat us at each polling interval. the interrupt endpoint is imple- mented via the ctl module. when the endpoint is accessed, the interrupt packet specified in table 4-2 is presented to the host. if there is no interrupt status to report, the device responds with a nack. the interrupt status can be cleared by writing to interrupt status register (int_sts) . 4.3.1.4 endpoint 0 (control) the control endpoint is handled by the ctl (usb control) module. the ctl module is responsible for handling usb standard commands, as well as usb vendor commands. in order to support these commands, the ctl must compile a variety of statistics and store the programmable portions of the usb descriptors. the supported usb commands can be found in section 4.3.2, "usb standard commands" . table 4-2: interrupt packet format bits description 31:20 reserved 19 macrto_int 18 rx fifo has frame. the rx fifo has at least one complete ethernet frame. 17 txstop_int 16 rxstop_int 15 phy_int 14 txe 13 tdfu 12 tdfo 11 rxdf_int 10:0 gpio_int note: the polling interval is static and set through th e eeprom. the host can change the polling interval by updating the cont ents of the eeprom an d resetting the part. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 35 lan9730/lan9730i 4.3.1.5 usb command processing the udc is programmed to decode usb commands. after a standard command is decoded by the udc, it may be passed to the ctl for completion. the ctl is responsible for implementing the get descriptor and vendor commands. in order to implement the get descriptor command for stri ng descriptors, the ctl manages a 128 x 32 register file which stores the string values for language id, manufacturer id, product id, serial number, configuration, and inter- face. the rams contents is initialized via the eeprom, after a system reset occurs. when the udc decodes a get descriptor command, it will pass a pointer to the ctl. the ctl uses this pointer to deter- mine what the command is and how to fill it. 4.3.1.6 usb descriptors the following subsections describe the usb descriptors. 4.3.1.6.1 device descriptor the device descriptors are initialized based on values stored in eeprom. table 4-4 shows the default device descrip- tor values. note 4-1 the descriptor length and descriptor type for device descriptors specified in eeprom are dont cares and are always overwritten by hardware as 0x12 and 0x01, respectively. table 4-3: string desc riptor index mappings index string name 0 language id 1 manufacturer id 2 product id 3 serial number 4 configuration string 5 interface string table 4-4: device descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 12h note 4-1 size of the descriptor in bytes (18 bytes) 01h bdescriptortype 1 01h note 4-1 device descriptor (0x01) 02h bcdusb 2 0200h note 4-2 usb specification number which device complies to. 04h bdeviceclass 1 ffh yes class code 05h bdevicesubclass 1 00h yes subclass code 06h bdeviceprotocol 1 ffh yes protocol code 07h bmaxpacketsize 1 40h note 4-2 maximum packet size for endpoint 0 08h idvendor 2 0424h yes vendor id 0ah idproduct 2 9730h yes product id 0ch bcddevice 2 note 4-3 yes device release number 0eh imanufacturer 1 00h yes index of manufacturer string descriptor 0fh iproduct 1 00h yes index of product string descriptor 10h iserialnumber 1 00h yes index of serial number string descrip- tor 11h bnumconfigurations 1 01h note 4-2 number of possible configurations downloaded from: http:///
lan9730/lan9730i ds00001946a-page 36 ? 2012-2015 microchip technology inc. note 4-2 value is loaded from eeprom, but must be equal to t he default value in order to comply with the usb 2.0 specification and provide for no rmal device operation. specification of any other value will result in unwanted behavior and untoward operation. note 4-3 default value is dependent on device release. t he msb matches the device release and the lsb is hardcoded to 00h. the initial release value is 01h. 4.3.1.6.2 configuration descriptor the configuration descriptor is initializ ed based on values stored in eeprom. table 4-5 shows the default configura- tion descriptor values. note 4-4 value is loaded from eeprom, but must be equal to t he default value in order to comply with the usb 2.0 specification and provide for no rmal device operation. specification of any other value will result in unwanted behavior and untoward operation. note 4-5 the descriptor type for configurati on descriptors specified in eeprom is a dont care and is always overwritten by hardware as 0x02. note 4-6 default value is 01h in self-powered mode and fah in bus powered mode. table 4-5: configuration descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 09h note 4-4 size of the configuration descriptor in bytes (9 bytes) 01h bdescriptortype 1 02h note 4-5 configuration descriptor (0x02) 02h wtotallength 2 0027h note 4-4 total length in bytes of data returned (39 bytes) 04h bnuminterfaces 1 01h note 4-4 number of interfaces 05h bconfigurationvalue 1 01h note 4-4 value to use as an argument to select this configuration 06h iconfiguration 1 00h yes index of string descriptor describing this configuration 07h bmattributes 1 a0h yes bus powered and remote wakeup enabled. 08h bmaxpower 1 note 4-6 yes maximum power consumption is 500 ma. note: the rmt_wkp strap affects the def ault value of bmattributes. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 37 lan9730/lan9730i 4.3.1.6.3 interface descriptor 0 default table 4-6 shows the default value for interface descriptor 0. th is descriptor is initialized based on values stored in eeprom. note 4-7 value is loaded from eeprom, but must be equal to t he default value in order to comply with the usb 2.0 specification and provide for normal device operation. specification of any other value will result in unwanted behavior and untoward operation. 4.3.1.6.4 endpoint 1 (bulk-in) descriptor table 4-7 shows the default value for endpoint descriptor 1. this descriptor is not initialized from values stored in eeprom. note 4-8 512 bytes for hi-speed mode. table 4-6: interface descriptor 0 offset field size (bytes) default value loaded from eeprom description 00h blength 1 09h note 4-7 size of descriptor in bytes (9 bytes) 01h bdescriptortype 1 04h note 4-7 interface descriptor (0x04) 02h binterfacenumber 1 00h note 4-7 number identifying this interface 03h balternatesetting 1 00h note 4-7 value used to select alternative setting 04h bnumendpoints 1 03h note 4-7 number of endpoints used for this inter- face (less endpoint 0) 05h binterfaceclass 1 ffh yes class code 06h binterfacesubclass 1 00h yes subclass code 07h binterfaceprotocol 1 ffh yes protocol code 08h iinterface 1 00h yes index of string descriptor describing this interface table 4-7: endpoint 1 descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 07h no size of descriptor in bytes 01h bdescriptortype 1 05h no endpoint descriptor 02h bendpointaddress 1 81h no endpoint address 03h bmattributes 1 02h no bulk transfer type 04h wmaxpacketsize 2 note 4-8 no maximum packet size this endpoint is capable of sending. 06h binterval 1 00h no interval for polling endpoint data trans- fers. ignored for bulk endpoints downloaded from: http:///
lan9730/lan9730i ds00001946a-page 38 ? 2012-2015 microchip technology inc. 4.3.1.6.5 endpoint 2 (bulk-out) descriptor table 4-8 shows the default value for endpoint descriptor 2. this descriptor is not initialized from values stored in eeprom. note 4-9 512 bytes for hi-speed mode. 4.3.1.6.6 endpoint 3 (interrupt) descriptor table 4-9 shows the default value for endpoint de scriptor 3. only the binterval field of this descriptor is initialized from eeprom. note 4-10 this value is loaded from the eeprom. if no eeprom exists then this value defaults to 04h. table 4-8: endpoint 2 descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 07h no size of descriptor in bytes 01h bdescriptortype 1 05h no endpoint descriptor 02h bendpointaddress 1 02h no endpoint address 03h bmattributes 1 02h no bulk transfer type 04h wmaxpacketsize 2 note 4-9 no maximum packet size this endpoint is capable of sending. 06h binterval 1 00h no interval for polling endpoint data trans- fers. ignored for bulk endpoints table 4-9: endpoint 3 descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 07h no size of descriptor in bytes 01h bdescriptortype 1 05h no endpoint descriptor 02h bendpointaddress 1 83h no endpoint address 03h bmattributes 1 03h no interrupt transfer type 04h wmaxpacketsize 2 10h no maximum packet size this endpoint is capable of sending. 06h binterval 1 note 4-10 yes interval for polling endpoint data trans- fers. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 39 lan9730/lan9730i 4.3.1.6.7 other speed configuration descriptor the fields in this descriptor are derived from configurat ion descriptor information that is stored in the eeprom. note 4-11 value is loaded from eeprom, but must be equal to t he default value in order to comply with the usb 2.0 specification and provide for normal device operation. specification of any other value will result in unwanted behavior and untoward operation. note 4-12 default value is 01h in self-powered mode and fah in bus-powered mode. 4.3.1.6.8 device qu alifier descriptor the fields in this descriptor are de rived from device descrip tor information that is stored in the eeprom. table 4-10: other speed configuration descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 09h note 4-11 size of descriptor in bytes (9 bytes) 01h bdescriptortype 1 07h note 4-11 other speed configuration descrip- tor (0x07) 02h wtotallength 2 0027h note 4-11 total length in bytes of data returned (39 bytes) 04h bnuminterfaces 1 01h note 4-11 number of interfaces 05h bconfigurationvalue 1 01h note 4-11 value to use as an argument to select this configuration 06h iconfiguration 1 00h yes index of string descriptor describing this configuration 07h bmattributes 1 a0h yes bus powered and remote wakeup enabled. 08h bmaxpower 1 note 4-12 yes maximum power consumption is 500 ma. note: eeprom values are obtained for the configuration descriptor at the other usb speed. i.e., if the current operating speed is fs, then the hs configuratio n descriptor values are used, and vice-versa. note: the rmt_wkp strap affects the def ault value of bmattributes. table 4-11: device qualifier descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 0ah no size of descriptor in bytes (10 bytes) 01h bdescriptortype 1 06h no device qualifier descriptor (0x06) 02h bcdusb 2 0200h note 4-13 usb specification number which device complies to. 04h bdeviceclass 1 ffh yes class code 05h bdevicesubclass 1 00h yes subclass code 06h bdeviceprotocol 1 ffh yes protocol code 07h bmaxpacketsize0 1 40h note 4-13 maximum packet size 08h bnumconfigurations 1 01h note 4-13 number of other speed configura- tions 09h reserved 1 00h no must be zero downloaded from: http:///
lan9730/lan9730i ds00001946a-page 40 ? 2012-2015 microchip technology inc. note 4-13 value is loaded from eeprom, but must be equal to t he default value in order to comply with the usb 2.0 specification and provide for no rmal device operation. specification of any other value will result in unwanted behavior and untoward operation. 4.3.1.6.9 string descriptors string index = 0 (langid) string indices 1-5 note: eeprom values are from the device descriptor (including any eeprom override ) at the opposite hs/fs operating speed. i.e., if the current operating speed is hs, then device qualifier data is based on the fs device descriptor , and vice-versa. table 4-12: langid string descriptor offset field size (bytes) default value loaded from eeprom description 00h blength 1 04h no size of langid descriptor in bytes (4 bytes) 01h bdescriptortype 1 03h no string descriptor (0x03) 02h langid 2 none yes must be set to 0x0409 (us english). note: if there is no valid/enabl ed eeprom, or if all string lengths in the eeprom are 0, then there are no strings, so any host attempt to read the langid string will retu rn stall in the data stage of the control transfer. if there is a valid/enabled eeprom, a nd if at least one of t he string lengths in the eeprom is not 0, then the value contained at eeprom addresses 0x0a-0x0b will be returned. these must be 0x0409 to allow for proper device operation. note: the device ignores the langid field in control reads of strings, and will not return the string (if it exists), regardless of whether the requested langid is 0x0409 or not. table 4-13: string descriptor (indices 1-5) offset field size (bytes) default value loaded from eeprom description 00h blength 1 none yes size of the string descriptor in bytes (4 bytes) 01h bdescriptortype 1 none yes string descriptor (0x03) 02h unicode string 2*n none yes 2 bytes per unicode character, no trail- ing null. note: if there is no valid/enabled eeprom, or if the corre sponding string length and offset in the eeprom for a given string index are zero, then that string does no t exist, so any host attempt to read that string will return stall in the data stage of the control transfer. note: the device returns whatever bytes are in the designate d eeprom area for each of these strings. it is the responsibility of the eeprom programmer to correctly set the blength and bdescriptortype fields in the descriptor consistent with the byte length specified in the corresponding eeprom locations. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 41 lan9730/lan9730i 4.3.1.7 statistics the ctl tracks the statistics listed in ta b l e 4 - 1 4 . the statistics are read via the get statistics vendor command. error conditions are indicated via the rx status word, table 4-40 , or the tx status word, table 4-44 . note: the counters are snapshot when fulfilling the command request. th e statistics counters rollover. table 4-14: statistic counters name description size (bits) rx good frames number of good rx frames received. includes frames dropped by the fct. 32 rx crc errors number of rx frames received with crc-32 errors. a crc error is indicated when the crc error flag is set and the dribbling bit flag is not set. 20 rx runt frame errors number of rx frames received with a length of less than 64 bytes and a crc error. 20 rx alignment errors number of rx frames received with alignment errors. an alignment error is indicated by the presence of the crc error flag and the dribbling bit flag is set. 20 rx frame too long error number of rx frames received with a length greater than the pro- grammed maximum ethernet frame size. 20 rx later collision error number of rx frames received where a late collision has occurred. 20 rx bad frames total number of errored ethernet fram es received. this counter does not include rx fifo dropped frames. 20 rx fifo dropped frames number of rx frames dropped by the fc t due to insufficient room in the rx fifo. if an rx fifo dropped frame has an ethernet error, i.e., crc error, it must only be counted by the rx fifo dropped frames counters. 20 tx good frames number of successfully transmitted tx frames. does not count pause frames. 32 tx pause frames number of successfully transmitted pause frames. 20 tx single collisions number of successfully transmitted frames with one collision. 20 tx multiple collisions number of successfully transmitted frames with more than one collision. 20 tx excessive collision errors number of transmitted frames aborted due to excessive collisions. 20 tx late collision errors number of transmitted frames aborted due to late collisions. 20 tx buffer underrun errors number of transmitted frames aborted due to tx buffer under run. 20 tx excessive deferral errors number of transmitted frames aborted due to excessive deferrals. 20 tx carrier errors number of frames transmitted in whic h the carrier signal was lost or in which the carrier signal was not present. 20 tx bad frames total number of errored et hernet frames transmitted. 20 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 42 ? 2012-2015 microchip technology inc. 4.3.2 usb standard commands this section lists the formats of the supported usb standa rd commands. the set descriptor, set interface, and synch frame commands are not supported. 4.3.2.1 clear feature this command clears the stall status of the ta rgeted endpoint or the device remote wakeup. note 4-14 set to 00h to clear device remote wakeup event. set to 02h to clear the endpoint stall status. note 4-15 when the bmrequesttype field specifies an endpoint, the windex field selects the endpoint (0, 1, 2, or 3) targeted by the command. 4.3.2.2 get configuration table 4-15: format of clear feature setup stage offset field value 0h bmrequesttype note 4-14 1h brequest 01h 2h wvalue selects feature to clear. 4h windex note 4-15 6h wlength 00h table 4-16: format of get configuration setup stage offset field value 0h bmrequesttype 80h 1h brequest 08h 2h wvalue 00h 4h windex 00h 6h wlength 01h table 4-17: format of get configuration data stage offset field 0h returns bconfigurationvalue downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 43 lan9730/lan9730i 4.3.2.3 get descriptor note 4-16 selects descriptor type. the supported descriptors fo r this command are device, configuration, string, device qualifier, and other speed configuration. note 4-17 set to zero or language id. 4.3.2.4 get interface table 4-18: format of get descriptor setup stage offset field value 0h bmrequesttype 80h 1h brequest 06h 2h wvalue note 4-16 4h windex note 4-17 6h wlength length of descriptor note: the interface and endpoint descriptors are not s upported by this command. the udc will stall these requests. table 4-19: format of get interface setup stage offset field value 0h bmrequesttype 81h 1h brequest 0ah 2h wvalue 00h 4h windex 00h 6h wlength 01h table 4-20: format of get interface data stage offset field 0h alternate setting note: the device only supports a single interface. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 44 ? 2012-2015 microchip technology inc. 4.3.2.5 get status 4.3.2.5.1 device status 4.3.2.5.2 endpoint 1 status (bulk-in) table 4-21: format of get status (device) setup stage offset field value 0h bmrequesttype 80h 1h brequest 00h 2h wvalue 00h 4h windex 00h 6h wlength 02h table 4-22: format of get status (device) data stage offset field 0h {00h, 0h, 00b, remote wakeup, self powered} table 4-23: format of get status (endpoint 1) setup stage offset field value 0h bmrequesttype 82h 1h brequest 00h 2h wvalue 00h 4h windex 81h 6h wlength 02h table 4-24: format of get status (endpoint 1) data stage offset field 0h {00h, 0h, 000b, stall status} downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 45 lan9730/lan9730i 4.3.2.5.3 endpoint 2 status (bulk-out) 4.3.2.5.4 endpoint 3 status (interrupt) 4.3.2.5.5 set address table 4-25: format of get status (endpoint 2) setup stage offset field value 0h bmrequesttype 82h 1h brequest 00h 2h wvalue 00h 4h windex 02h 6h wlength 02h table 4-26: format of get status (endpoint 2) data stage offset field 0h {00h, 0h, 000b, stall status} table 4-27: format of get status (endpoint 3) setup stage offset field value 0h bmrequesttype 82h 1h brequest 00h 2h wvalue 00h 4h windex 83h 6h wlength 02h table 4-28: format of get status (endpoint 3) data stage offset field 0h {00h, 0h, 000b, stall status} table 4-29: format of set address setup stage offset field value 0h bmrequesttype 00h 1h brequest 05h 2h wvalue device address 4h windex 00h 6h wlength 00h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 46 ? 2012-2015 microchip technology inc. 4.3.2.5.6 set feature this command sets the stall feature for all supported endpoints. it also sup ports the device remote wakeup feature and test mode. 4.3.2.5.7 set configuration the device supports only one configuration. an occurrence of this command places the device into the configured state. since only one configuration is supported, 01h is the only supported configuration value. 4.3.2.5.8 set interface only one interface is supported by the device. therefore, th is command is of marginal use. if the command is issued with an alternative setting of 00h and interface setting of 00h, as shown in table 4-32 , the device responds with an ack. otherwise it responds with a stall handshake. table 4-30: format of set feature setup stage offset field value 0h bmrequesttype 00h for device 02h for endpoint 1h brequest 03h 2h wvalue 01h for device_remote_wakeup 00h for endpoint_halt 02h for est_mode 4h windex 00h for device remote wakeup 00h for test_mode interface endpoint number for halt 6h wlength 00h table 4-31: format of set configuration setup stage offset field value 0h bmrequesttype 00h 1h brequest 09h 2h wvalue configuration value 4h windex 00h 6h wlength 00h table 4-32: format of set interface setup stage offset field value 0h bmrequesttype 01h 1h brequest 0bh 2h wvalue 00h 4h windex 00h 6h wlength 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 47 lan9730/lan9730i 4.3.3 usb vendor commands the device implements several vendor specific commands in or der to access csrs and efficiently gather statistics. the vendor commands allow direct access to systems csrs and mac csrs. 4.3.3.1 register write command the commands allows the host to write a single register. burst writes are not supporte d. all writes are 32-bits. 4.3.3.2 register read command the commands allows the host to read a single register. burst reads are not supported. all reads return 32-bits. note: when in the normal state, accesses to the mac csrs are stalled. table 4-33: format of regi ster write setup stage offset field value 0h bmrequesttype 40h 1h brequest a0h 2h wvalue 00h 4h windex {0h, csr address[11:0]} 6h wlength 04h table 4-34: format of register write data stage offset field 0h register write data [31:0] table 4-35: format of register read setup stage offset field value 0h bmrequesttype c0h 1h brequest a1h 2h wvalue 00h 4h windex {0h, csr address[11:0]} 6h wlength 04h table 4-36: format of register read data stage offset field 0h register read data [31:0] downloaded from: http:///
lan9730/lan9730i ds00001946a-page 48 ? 2012-2015 microchip technology inc. 4.3.3.3 get statistics command the get statistics command returns the entire contents of the statistics rams. the windex field is used to select the rx or tx statistics. note 4-18 0b - retrieves rx statistics. 1b - retrieves tx statistics. note 4-19 28h for rx statistics. 30h for tx statistics. note: the contents of the statistics ram is snapshot when fulfilling the command reques t. the statistics counters rollover, hence the ram is not cleared. table 4-37: format of get statistics setup stage offset field value 0h bmrequesttype c0h 1h brequest a2h 2h wvalue 00h 4h windex note 4-18 6h wlength note 4-19 table 4-38: format of get statistics data stage (rx) offset field 00h rx good frames 04h rx crc errors 08h rx runt frame errors 0ch rx alignment errors 10h rx frame too long error 14h rx later collision error 18h rx bad frames 1ch rx fifo dropped frames 20h reserved 24h reserved table 4-39: format of get statistics data stage (tx) offset field 00h tx good frames 04h tx pause frames 08h tx single collisions 0ch tx multiple collisions 10h tx excessive collision errors 14h tx late collision errors 18h tx buffer underrun errors 1ch tx excessive deferral errors 20h tx carrier errors 24h tx bad frames 28h reserved 2ch reserved downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 49 lan9730/lan9730i 4.4 fifo controller (fct) the fifo controller uses a 28 kb internal sram to buffer rx and tx traffic. 20 kb are allocated for received ethernet- usb traffic (rx buffer), while 8 kb are allocated for usb-ethernet traffic (tx bu ffer). bulk-out packets from the usb controller are directly stored into the tx buffer. the fct is responsible for extracting ethernet frames from the usb packet data and passing the frames to the mac. ethernet frames are directly stor ed into the rx buffer and become the basis for bulk-in packets. the fct passes the stored da ta to the utx in blocks typically 512 bytes in size. 4.4.1 rx path (ethernet -> usb) the 20 kb rx fifo buffers ethernet frames received from the tli. the utx extrac ts these frames from the fct to form usb bulk-in packets. the host drivers will ultimately reassemble the ethernet frames from the usb packets. the fct manages the writing of data into the rx fifo through the use of two pointers - the rx_wr_ptr and the rx_wr_h- d_ptr. the rx_wr_ptr is used to write ethernet frame data into the fifo. the rx_wr_hd_ptr points to the location prior to the first dword of the frame. it is used to write the rx status word received from the tli, upon completion of a frame transaction. this status word contains status informa tion associated with the frame and the frame transaction. figure 4-4 illustrates how a frame is stored in the fifo, along with pointer usage. when the rx tli signals that it has data ready, the rx tli controller starts passing the rx packet data to the fct. the fct updates the rx fifo pointers as the data is written into the fifo. the last transfer from the tli is the rx status word. the fct may insert 0-3 bytes at the start of the ethernet fram e. the value of the rx data offset (rxdoff) field of the hardware configuration register (hw_cfg) determines the number of bytes inserted. a received ethernet frame is not visible to the utx until the complete frame, including the rx status word, has been written into the rx fifo. this is due to the fact that the frame may have to be removed via a rewind (pointer adjustment), in case of an error. such is the case when a fifo overflow condition is detected as t he frame is being received. the fct may also be configured to rewind errored frames. refer to section 4.4.1.1, "rx error detection" for further details. figure 4-4: rx fifo storage rx status word rx ethernet frame 0 rx status word rx ethernet frame 1 rx_rd_ptr rx_wr_hd_ptr rx ethernet frame 2 rx_wr_ptr after the complete ethernet frame is written, the size and status is updated at the location pointed to by the write head pointer. the write head pointer will then advance to the starting location for the next ethernet frame. the read head pointer is used for implementing rewinds of usb packets. rx_rd_hd_ptr usb packet 0 usb packet 1 usb packet 2 usb packet 3 fifo data is available for transmit only after a complete ethernet frame is received and stored. therefore, the rx fifo size will not reflect partially received packets. rx fifo size byte padding inserted by the fct. this amount is determined by rxdoff[1:0] additional padding may be inserted by the utx. the unused bytes in the first and last dwords are ignored by the host. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 50 ? 2012-2015 microchip technology inc. 4.4.1.1 rx error detection the fct can be configured to drop ethernet frames w hen certain error conditions occur. the setting of the discard errored received et hernet frame (drp) bit of the hardware configuration register (hw_cfg) on page 125 deter- mines if the frame will be retained or dropped. error condition s are indicated in the rx status word. the following error conditions are tracked by the tli: crc error collision seen frame too long runt frame refer to section 4.3.1.7, "statistics" for more details on the error conditions tracked by the device. the fct also drops frames when it detects a fifo overflow condition. this occurs when the fifo full condition occurs while a frame is being received. the fct also maintains a count of the number of times a fifo overflow condition has occurred. dropping an ethernet frame is implemen ted by rewinding the received frame. a write side rewind is implemented by setting the rx_wr_ptr to be equal to the rx_wr_hd_ptr. si milarly, a read side rewind is implemented by setting the rx_rd_ptr to be equal to the rx_rd_hd_ptr. for the case where the frame is dropped due to overflow, the fct ignores the remainder of the frame. it will not begin writing into the rx fifo again until the next frame is received. in the read direction, the fct must also support rewinds fo r the utx. this is needed for the case where the usb bulk- out packet is not successfully received by the host and needs to be retransmitted. 4.4.1.2 rx status format table 4-40 illustrates the format of the rx status word. table 4-40: rx status word format bits description 31 reserved 30 filtering fail when set, this bit indicates that the associ ated frame failed the address recognizing filtering. 29:16 frame length the size, in bytes, of the corresponding received frame. 15 error status (es) when set, this bit indicates that the tli has reported an error. this bit is the logical or of bits 11, 7, 6, 1 in this status word. 14 reserved 13 broadcast frame when set, this bit indicates that the received frame has a broadcast address. 12 length error (le) when set, this bit indicates that the actual leng th does not match with the length/type field of the received frame. 11 runt frame when set, this bit indicates that frame was pr ematurely terminated before the collision window (64 bytes). runt frames are passed on to the host only if the pass bad frames bit mac_cr bit [16] is set. 10 multicast frame when set, this bit indicates that the received frame has a multicast address. 9:8 reserved 7 frame too long when set, this bit indicates that the frame length exceeds the maximu m ethernet specification of 1518 bytes. this is only a frame too long indication an d will not cause the frame reception to be truncated. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 51 lan9730/lan9730i 4.4.1.3 flushing the rx fifo the device allows for the host to flush the entire contents of the fct rx fifo. when a flush is activated, the read and write pointers of the rx fifo are returned to their reset state. before flushing the rx fifo, the devices receiver must be stop ped, as specified in section 4.4.1.4 . once the receiver stop completion is confirmed, the receive fifo flush bit can be set in the receive configuration register (rx_cfg) on page 123 to initiate the flush operation. this bi t is cleared after th e flush is complete. 4.4.1.4 stopping and starting the receiver to stop the receiver, the host must clear the receiver enable (rxen) bit in the mac control register (mac_cr) on page 163 . when the receiver is halted, the rxstop_int will be pulsed. once stopped, the host can optionally clear the rx status and rx fifos. the host must re -enable the receiver by setting the rxen bit. 4.4.2 tx path (usb -> ethernet) the 8 kb tx fifo buffers usb bulk-out packets received by the urx. the fct is responsible for extracting the ether- net frames embedded in the usb bulk-out packets and passing them to the tli. the ethernet frames are segmented across the usb packets by the host drivers. the fct manages the writing of data into the tx fifo through the use of two po inters - the tx_wr_ptr and the tx_wr_h- d_ptr. these pointers are used to manage the storing of usb bulk-out packets. they support rewinding the stored usb packet, in the event that the bulk-out packet is errored and needs to be retransmitted by the host. the write side of the fct does not perform any processing on the usb packet data. t he read side of the tx fifo is responsible for extract- ing the ethernet frames. the ether net frames may be split across multiple buffers, as shown in figure 4-5 . 6 collision seen when set, this bit indicates that the frame has seen a collision after the collision window. this indicates that a late collision has occurred. 5 frame type when set, this bit indicates that the frame is an et hernet-type frame (l ength/type field in the frame is greater than 1500). when reset, it indicates the incomi ng frame was an 802.3 type frame. this bit is not set for runt frames less than 14 bytes. 4 receive watchdog time-out when set, this bit indicates that the incoming frame is greater than 2048 bytes through 2560 bytes, therefore expiring the receive watchdog timer. 3 mii error when set, this bit indicates that a receive error (r x_er asserted) was detected during frame reception. 2 dribbling bit when set, this bit indicates that the frame contai ned a no-integer multiple of 8 bits. this error is reported only if the number of dribbling bits in the last byte is 4 in the mii operating mode, or at least 3 in the 10 mbps operating mode. this bit will not be set when the collision seen bit[6] is set. if set and the crc error[1] bit is reset, then the frame is considered to be valid. 1 crc error when set, this bit indicates that a crc error was detected. this bit is also set when the rx_er pin is asserted during the reception of a frame even though the crc may be correct. this bit is not valid if the received frame is a runt frame, or a late collision was detected or when the watchdog time-out occurs. 0 reserved table 4-40: rx status word format (continued) bits description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 52 ? 2012-2015 microchip technology inc. figure 4-5: tx fifo storage tx command a tx command b tx command a tx command b tx command a tx command b tx command a tx command b 23 byte payload 17 byte payload 9 byte payload 16 byte payload 65 byte ethernet frame tx_wr_ptr tx_wr_hd_ptr usb packet 0 usb packet 1 tx command a tx command b tx_rd_ptr unused bytes are indicated to the tli by controlling the byte enables. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 53 lan9730/lan9730i 4.4.2.1 tx command format as shown in figure 4-5 , each buffer starts with a two dword tx command. the tx command instructs the fct on the handling of the associated buffer. the command precedes the data to be transmitted. the tx command is divided into two, 32-bit words; tx command a and tx command b. both tx command a and tx command b are required for each buffer in a given packet. tx command b must be iden- tical for every buffer in a given packet, with the exception of the tx checksum enable (ck) bit. if the tx command b dwords do not match, the fct will assert the transmitter error (txe) flag. frame boundaries are delineated using control bits within the tx command. the frame length field in tx command b specifies the number of bytes in the a ssociated frame. all frame length fields must have the same value for all buffers in a given frame. hardware compares the frame length field and the actual amount of data re ceived. if the actual frame length count does not match the frame length field, an error has occurred. the formats of tx command a and tx command b are shown in table 4-41 and table 4-42 , respectively. table 4-41: tx command a format bits description 31:18 reserved 17:16 data start offset (bytes) this field specifies the offset of the first byte of tx data. the offset value ranges between 0 bytes and 3 bytes. 15:14 reserved 13 first segment when set, this bit indicates that the associ ated buffer is the first segment of the frame. 12 last segment when set, this bit indicates that the associ ated buffer is the last segment of the frame. 11 reserved 10:0 buffer size (bytes) this field indicates the number of bytes contai ned in the buffer following the two command dwords (tx command a and tx command b). this value, along with the data start offset field, is used by the fct to determine how many extra bytes were added to the end of the buffer. a running count is also maintained in the fct of the cumulative buffer sizes for a given frame. this cumulative value is com- pared against the frame length field in the tx comm and b word and if they do not correlate, the txe flag is set. the buffer size specified does not include bytes added due to the end of buffer alignment padding or the data start offset field. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 54 ? 2012-2015 microchip technology inc. 4.4.2.2 tx data format the tx data section begins at the third dword in the tx buffer (after tx command a and tx command b). the loca- tion of the first byte of valid buffer dat a to be transmitted is specified in the data start offset field of tx command a. table 4-43, "tx data start offset" shows the correlation between the setting of the lsbs in the data start offset field and the byte location of the first valid data byte. tx data is contiguous until the end of the buffer. the buf fer may end on a byte boundary. unused bytes at the end of the packet will not be sent to the tli for transmission. 4.4.2.3 tx buffer fragmentation rules transmit buffers must adhere to the following rules: each buffer may start and end on any arbitrary byte alignment. the first buffer of any trans mit packet can be any length. middle buffers (i.e., those with first segment = last segm ent = 0) must be greater than , or equal to 4 bytes in length. the final buffer of any transmit packet can be any length. table 4-42: tx command b format bits description 31:15 reserved 14 tx checksum enable (ck) if this bit is set in conjunction with the first se gment bit (fs) in tx command a and the tx checksum offload engine enable bit (txcoe_en) in the checksum offload engine control register (coe_cr), the tx checksum offload engine (txcoe) will calculate an l3 ch ecksum for the associated frame. note: this bit only needs to be set for the first buffer of a frame. 13 add crc disable when set, the automatic addition of the crc is disabled. 12 disable ethernet frame padding when set, this bit prevents the automatic addition of padding to an ethernet frame of less than 64 bytes. the crc field is also added despit e the state of the add crc disable field. 11 reserved 10:0 frame length (bytes) this field indicates the total number of bytes in th e current frame. this length does not include the off- set or padding. if the frame length field does not match the actual nu mber of bytes in the frame, the transmitter error (txe) flag will be set (in the interrupt status register (int_sts) and the interrupt endpoint). this value is read by the tx fifo cont roller, and is used to determine the amount of data that must be moved from the tx dat a fifo into the tli block. if th e byte count is not aligned to a dword boundary, the tx fifo controller will issue the correct byte enables to the tli layer during the last write. invalid bytes in the last dwo rd will not be passed to the tli for transmission. table 4-43: tx data start offset data start offset[1:0] 11 10 01 00 first tx data byte d[31 :24] d[23:16] d[15:8] d[7:0] downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 55 lan9730/lan9730i 4.4.2.4 fct actions the fct performs basic sanity che cks on the correctness of the buffer configurat ion, as described in section 4.4.2.5, "tx error detection" . errors in this regard indicate t he tx path is out of sync, which is catastrophic and requires a reini- tialization of the tx path. the fct performs the following steps w hen extracting an ethernet frame: strip out tx command a strip out tx command b account for the byte offset at the beginning of the frame. based upon the buffer size and datastartoffset[1:0] field of tx command a, the fct can numerica lly determine any unused bytes in the first and last word of the buffer. when transferring these respective dwords to the tli, the fct adjusts the byte enables accordingly. unlike the write side, the read side of the tx fifo does not need to support rewi nds. errors are reported via the trans- mitter error (txe) flag, which is visible to the host via the interrupt endpoint and is also set in the interrupt status reg- ister (int_sts) . 4.4.2.5 tx error detection as previously stated, both tx command a and tx command b are required for each buffer in a given frame. tx com- mand b must be identical for every buffer in a given frame, with the exception of the tx checksum enable (ck) bit. if the tx command b words do not match, then the tx path is out of sync and the fct asserts the transmitter error (txe) flag. similarly, the fct numerically adds up the size of the frame s buffers. if there is a numer ical mismatch, the tx path is out of sync and the fct asserts the transmitter error (txe) flag. the following error conditions are tracked by the fct: missing fs - the expected first buffer of a frame does not have the fs bit set. unexpected fs - the fs bit is set when the total size of buffers so far opened is less than the frame size. missing ls - the total size of the buffers opened is equal to or exceeds the size of the frame. the fct expects this buffer to have the ls bit set and it is not set. unexpected ls - the ls bit is set when the aggregate total size of descriptor buffers so far opened is less than the frame size. buffer size is zero error - the buffer length field is zero. buffer size error - the total sum of the buffers received is not equal to the frame length. note: when a packet is split into multiple buffers, each successive buffers data payload may begin on any arbi- trary byte. note: the fct can be configured to stall the bulk-out pipe when a transmit error is detected. this is accom- plished via the stall bulk-out pipe disable (sbp) bit of the hardware configuration register (hw_cfg) . refer to section 6.3.5, "hardware configuration register (hw_cfg)" for further details. note: a tx error is a catastrophic condition. the device should be reset in order to recover from it. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 56 ? 2012-2015 microchip technology inc. 4.4.2.6 tx status format after an ethernet frame is transmitted, the tli returns th e tx status word to the fct, as illustrated in table 4-44 . the contents of the tx status word is used for statistics generation and in terrupt status creation. refer to section 4.3.1.7, "statistics" and section 6.3.2, "interrupt status register (int_sts)" for further details. table 4-44: tx status word format bits description 31:16 reserved 15 error status (es) when set, this bit indicates that the tli has reported an error. this bit is the logical or of bits 11, 10, 9, 8, 2, 1 in this status word. 14:12 reserved 11 loss of carrier when set, this bit indicates the loss of carrier during transmission. 10 no carrier when set, this bit indicates that the carrier signal from the transceiver was not present during transmis- sion. 9 late collision when set, indicates that the packet transmission was aborted after the collision window of 64 bytes. 8 excessive collisions when set, this bit indicates that the transmission was aborted after 16 collisions while attempting to transmit the current packet. 7 reserved 6:3 collision count this counter indicates the number of collisions that occurred before the packet was transmitted. it is not valid when excessive collisions (bit 8) is also set. 2 excessive deferral if the deferred bit is set in the control register, the setting of the excessive deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times during transmission. 1 underrun error when set, this bit indicates that the transmitter a borted the associated fram e because of an underrun condition on the tx data fifo. tx underrun will cause the assertion of the tdfu flag in the interrupt status register (int_sts) and the interrupt endpoint. 0 deferred when set, this bit indicates that the current packet transmission was deferred. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 57 lan9730/lan9730i 4.4.2.7 transmit examples 4.4.2.7.1 tx example 1 in this example a single, 1064-byte ethernet frame will be transm itted. this packet is divided into three buffers. the three buffers are as follows: buffer 0: 3 bytes data start offset 499 bytes of payload data buffer 1: 0 byte data start offset 503 bytes of payload data buffer 2: 2 bytes data start offset 62 bytes of payload data table 4-6 illustrates the tx command structure for this example, and also shows how data is passed to the tx data fifo. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 58 ? 2012-2015 microchip technology inc. figure 4-6: tx example 1 tx command a tx command b tx command a tx command b tx command a tx command b 1064 byte ethernet frame 503 byte payload 499 byte payload usb packet 0 usb packet 1 tx command a tx command b usb packet 2 62 byte payload tx command a data start offset = 3 first segment = 1 last segment = 0 buffer size = 499 tx command b frame length = 1064 tx command a data start offset = 0 first segment = 0 last segment = 0 buffer size = 503 tx command b frame length = 1064 tx command a data start offset = 2 first segment = 0 last segment = 1 buffer size = 62 tx command b frame length = 1064 .. . downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 59 lan9730/lan9730i 4.4.2.8 tx example 2 in this example, a single 183-byte ethernet frame will be transmitted. this packet is in a single buffer as follows: 2 bytes data start offset 183 bytes of payload data figure 4-7 illustrates the tx command structure for this exampl e, and also shows how data is passed to the tx data fifo. note that the packet resides in a single tx buffer, t herefore both the fs and ls bits are set in tx command a. 4.4.2.9 tx example 3 in this example a sing le, 111-byte ethernet fr ame will be transmitted with a tx c hecksum. this packet is divided into four buffers. the four buffers are as follows: buffer 0: 0 byte data start offset 4 bytes checksum preamble buffer 1: 3 bytes data start offset 79 bytes of payload data buffer 2: 0 byte data start offset 15 bytes of payload data buffer 3: 2 bytes data start offset 17 bytes of payload data figure 4-8 illustrates the tx command structure for this exampl e, and also shows how data is passed to the tx data fifo. figure 4-7: tx example 2 note: when enabled, the tx checksu m preamble is pre-pended to the data to be transmitted. the fs bit in tx command a, the tx checksum enable bit (ck) of tx command b, and the txcoe_en bit of the coe_cr register must all be set for the tx checksum to be generated. fs must not be set for subsequent fragments of the same packet. refer to section 4.5.8, "transmit che cksum offload engine (txcoe)" for further information. tx command a tx command b tx command a tx command b 183 byte ethernet frame 183 byte payload usb packet 0 tx command a data start offset = 2 first segment = 1 last segment = 1 buffer size = 183 tx command b frame length = 183 .. . downloaded from: http:///
lan9730/lan9730i ds00001946a-page 60 ? 2012-2015 microchip technology inc. 4.4.2.10 flushing the tx fifo the device allows for the host to flush t he entire contents of the fct tx fifo. when a flush is activated, the read and write pointers for the tx fifo ar e returned to their reset state. before flushing the tx fifo, the devices transmitter must be stopped, as specified in section 4.4.2.11 . once the trans- mitter stop completion is confirmed, the transmit fifo flush bit can be set in the transmit configuration register (tx_cfg) on page 124 . this bit is cleared afte r the flush is complete. figure 4-8: tx example 3 tx command a tx command b tx command a tx command b 115 byte ethernet frame 15 byte payload 79 byte payload usb packet 0 tx command a tx command b tx command a data start offset = 0 first segment = 1 last segment = 0 buffer size = 4 tx command b frame length = 111 tx checksum enable = 1 checksum preamble tx checksum location = 50 tx checksum start pointer = 14 .. . checksum preamble tx command a data start offset = 3 first segment = 0 last segment = 0 buffer size = 79 tx command b frame length = 111 tx checksum enable = 1 tx command a tx command b tx command a tx command b tx command a data start offset = 0 first segment = 0 last segment = 0 buffer size = 15 tx command b frame length = 111 tx checksum enable = 1 tx command a data start offset = 2 first segment = 0 last segment = 1 buffer size = 17 tx command b frame length = 111 tx checksum enable = 1 17 byte payload downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 61 lan9730/lan9730i 4.4.2.11 stopping and starting the transmitter to halt the transmitter, the host must set the stop transmitter (stop_tx) bit in the tx_cfg register. the transmitter will finish sending the current frame (if there is a frame tr ansmission in progress). when the transmitter has received the tx status for the current frame, it will clear the stop _tx and tx_on bits in the tx_cfg register, and will pulse txstop_int. once stopped, the host can optionally fl ush the tx fifo, and can optionally di sable the mac by clearing txen. the host must re-enable the transmitter by setting the tx_on and txen bits. if there are fr ames pending in the tx fifo (i.e., the tx fifo was not purged), t he transmission will resume with this data. 4.4.3 arbitration the fct must arbitrate access to the rx and tx fifos to th e urx, utx, tli rx, and tli tx. highest priority is always given to the usb. the tli rx/tx can be wait stated as fr ames buffering exists in the tli (2 kb tx, 128 byte rx). fct strict priority order: 1. urx request (bulk-out packet) 2. utx request (bulk-in packet) 3. tli rx (received ethernet frame) 4. tli tx (transmitt ed ethernet frame) 4.5 10/100 ethernet mac the ethernet media access controller (mac) incorporates the essential protocol require ments for operating an ether- net/ieee 802.3-compliant node and provides an interface bet ween the host subsystem and the internal ethernet phy. the mac can operate in either 100 mbps or 10 mbps mode. the mac operates in both half-duplex and full-duplex modes. when operating in half-duplex mode, the mac complies fully with section 4 of iso/iec 8802-3 (ansi/ieee standard) and ansi/ieee 802.3 standards. when operating in full- duplex mode, the mac complies with ieee 802.3x full-duplex operation standard. the mac provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. these features include the abilit y to disable retries after a collision, dynamic fcs (frame check sequence) generation on a frame-by -frame basis, automatic pad field inse rtion and deletion to enforce minimum frame size attributes, layer 3 checksum calculation for transmit and receive operations, and automatic retransmission and detection of collision frames. the mac can sustain transmission or reception of minimally-s ized back-to-back packets at full line speed with an inter- packet gap (ipg) of 9.6 microseconds for 10 mbps and 0.96 microseconds for 100 mbps. the primary attributes of the mac function are: transmit and receive message data encapsulation framing (frame boundary delimitation, frame synchronization) error detection (physical medium transmission errors) media access management medium allocation (collision detection, except in full-duplex operation) contention resolution (collision handli ng, except in full-duplex operation) flow control during full-duplex mode decoding of control frames (pause co mmand) and disabling the transmitter generation of control frames interface to the internal phy and optional external phy checksum offload engine for calculation of layer 3 transmit and receive checksum note: the tx stop mechanism described here assumes that the mac will return a status for every tx frame. note: by nature of the usb bus and udc operation, the urx and utx do not request bandwidth simultaneously. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 62 ? 2012-2015 microchip technology inc. the transmit and receive data paths are separate within the device from the mac to host interface, allowing the highest performance, especially in full-duplex mode. payload data as well as transmit and receive status are passed on these buses. a third internal bus is used to access the macs control and status registers (csrs). this bus is also accessible from the host. on the backend, the mac interfaces wi th the 10/100 phy through an mii (media independent interface) port which is internal to the device. in addition, there is an external mii interface supporting optional phy devices. the mac csr's also provide a mechanism for accessing the phys internal r egisters through the internal smi (serial management inter- face) bus. the receive and transmit fifos allow increased packet buf fer storage to the mac. t he fifos are a conduit between the host interface and the mac through which all transmitted and received data and status information is passed. deep fifos allow a high degree of latency tolerance relative to the various transport and os software stacks reducing and minimizing overrun conditions. like the mac, the fifo s have separate receive and transmit data paths. 4.5.1 flow control the devices ethernet mac supports full-duplex flow control using the pause operation and c ontrol frame. it also sup- ports half-duplex flow control using back pressure . in order for flow control to be invoked, the flow control enable (fcen) bit of the flow control register (flow) must be set. 4.5.1.1 full-duplex flow control the pause operation inhibits data transmission of data fram es for a specified period of ti me. a pause operation consists of a frame containing the globally assigned multicast a ddress (01-80-c2-00-00-01), the pause opcode, and a param- eter indicating the quantum of slot time (512 bit times) to inhibit data transmissions. the pause parameter may range from 0 to 65,535 slot times. the ethe rnet mac logic, on receiving a frame with the reserved multicast address and pause opcode, inhibits data frame transmissions for the length of time indicated. if a pause request is received while a transmission is in progress, then the pause will take effect after the transmission is complete. control frames are received and processed by the mac and are passed on. the device will automatically transmit p ause frames based on the settings of the automatic flow control configuration register (afc_cfg) and the flow control register (flow) . when the rx fifo reaches the level set in the automatic flow control high level (afc_hi) field of afc_cfg, the device will transmit a pause frame. the pause time field that is transmitted is set in the pause time (fcpt) field of the flow register. when the rx fifo drops below the level set in the automatic flow control low level (afc_lo) field of afc_cfg, the device will automatically transmit a pause frame with a pause time of zero. the device will only send another pause frame when the rx fifo level falls below afc_lo and then exceeds afc_hi again. 4.5.1.2 half-duplex flow control (backpressure) in half-duplex mode, back pressure is used for flow control. whenever the rx fifo crosses a certain threshold level, the mac starts sending a jam signal. the mac transmit logic enters a state at the end of current transmission (if any), where it waits for the beginning of a received frame. once a new frame starts, the mac starts sending the jam signal, which will result in a collision. after sensing the collision, the remote station will back off its transmission. the mac con- tinues sending the jam signal to make other stations def er transmission. the mac only generates this collision-based back pressure when it receives a new frame, in order to avoid any late collisions. the device will automatically assert back pressure based on the setting of the automatic flow control configuration register (afc_cfg) . when the rx fifo reaches the level set by automatic flow control high level (afc_hi) field of afc_cfg, the back pressure duration timer will start. the device will assert back pressu re for any received frames, as defined by the values of the fcany, fcadd, fcmult and fcbrd control bits of afc_cfg. this continues until the back pressure duration timer reaches the time specified by the back_dur field of afc_cfg. after the back_dur time period has elapsed, the receiver will accept o ne frame. if, after receiving one rx frame, the rx fifo is still above the threshold set in the automatic flow control low level (afc_lo) field of afc_cfg, the device will again start the back pressure duration timer and will assert back pressure for subsequent frames, repeating the pro- cess described here until the rx data fifo level drops below the afc_lo setting. if t he rx fifo drops below afc_lo before the back pressure duration timer has expired, the timer will immediately reset and back pressure will not be asserted until the rx fifo level exceeds afc_hi. if the afc_lo value is set to all ones (0xff) and the afc_hi value is set to all zeros (0x00), the flow controller will assert back pressure for received frames as if the afc_hi threshold is always exceeded. this mechanism can be used to generate software-controlled flow control by enabling and disabling the fcany, fcadd, fcmult and fcbrd bits. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 63 lan9730/lan9730i 4.5.2 virtual lo cal area network (vlan) support virtual local area networks or vlans, as defined within the ieee 802.3 standard, provid e network administrators one means of grouping nodes within a larger network into broadcast domains. to implement a vlan, four extra bytes are added to the basic ethernet packet. as shown in figure 4-9 , the four bytes are inserted after the source address field and before the type/length field. the first two bytes of the vlan tag identify the tag, and by convention are set to the value 0x8100. the last two bytes identify th e specific vlan associated with the pack et; they also provide a priority field. the device supports vlan-tagged packets. it provides two registers which are used to identify vlan-tagged packets. one register should normally be set to the conventional vlan id of 0x8100. the other register provides a way of iden- tifying vlan frames tagged with a proprietary (not 0x8100) iden tifier. if a packet arrives bearing either of these tags in the two bytes succeeding the source address field, the c ontroller will recognize the packet as a vlan-tagged packet. in this case, the controller increases the maximum allowed packet size from 1518 to 1522 bytes (normally the controller filters packets larger than 1518 bytes). this allows the packet to be received , and then processed by host software, or to be transmitted on the network. figure 4-9: vlan frame preamble (7 bytes) sof (1 byte) dest. addr. (6 bytes) source addr. (6 bytes) type (2 bytes) data (46 - 1500 bytes) fcs (4 bytes) ethernet frame (1518 bytes) preamble (7 bytes) sof (1 byte) dest. addr. (6 bytes) source addr. (6 bytes) type (2 bytes) data (46 - 1500 bytes) fcs (4 bytes) ethernet frame with vlan tag (1522 bytes) tpid (2 bytes) type (2 bytes) tpid (2 bytes) user priority (3 bits) cfi (1 bit) vlan id (12 bits) tag control information (tci) tag protocol d: \x81-00 indicates frame's priority canonical address format indicator vid: 12 bits defining the vlan to which the frame belongs downloaded from: http:///
lan9730/lan9730i ds00001946a-page 64 ? 2012-2015 microchip technology inc. 4.5.3 address filtering f unctional description the ethernet address fields of an ethernet packet, consists of two 6-byte fields: one for the destination address and one for the source address. the first bit of the destination address signifies whether it is a physical address or a multicast address. the devices address check logic filters the frame based on the ethernet receive filter mode that has been enabled. filter modes are specified based on the state of the control bits in table 4-45, "address filtering modes" , which shows the various filtering modes used by the ethernet mac function. these bits are defined in more detail in the mac control register. refer to section 6.4.1, "mac control register (mac_cr)" for more information on this register. if the frame fails the filter , the ethernet mac function does not receive the packet. the host has the option of accepting or ignoring the packet. 4.5.4 filtering modes 4.5.4.1 perfect filtering this filtering mode passes only incoming frames whose destination address field exactly matches the value pro- grammed into the mac address high register and the mac address low register. the mac address is formed by the concatenation of the above two regi sters in the mac csr function. 4.5.4.2 hash only filtering mode this type of filtering checks for incoming receive packets with either multicast or physi cal destination addresses, and executes an imperfect address filt ering against the hash table. during imperfect hash filtering, the destination address in the incoming frame is passed through the crc logic and the upper six bits of the crc register are used to index the cont ents of the hash table. the hash table is formed by merging the registers multicast hash table high and multicast hash table low in the mac csr function to form a 64-bit hash table. the most significant bit determines the register to be used ( high/low), while the other five bits determine the bit within the register. a value of 00000 selects bit 0 of the multi cast hash table low register and a value of 11111 selects bit 31 of the multicast hash table high register. table 4-45: address filtering modes mcpas prms invfilt ho hpfilt description 0 0 0 0 0 mac address perfect filtering only for all addresses. 0 0 0 0 1 mac address perfect filtering for physical address and hash filtering for multicast addresses. 0 0 0 1 1 hash filtering for physical and mul- ticast addresses. 0 0 1 0 0 inverse filtering x 1 0 x x promiscuous 1 0 0 0 x pass all multicast frames. frames with physical addresses are per- fect-filtered. 1 0 0 1 1 pass all multicast frames. frames with physical addresses are hash- filtered. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 65 lan9730/lan9730i 4.5.4.3 hash perfect filtering in hash perfect filtering, if t he received frame is a physical address, the devi ces packet filter block perfect filters the incoming frames destination field with the value programmed into the mac address high re gister and the mac address low register. if the incoming frame is a multicast frame, how ever, the devices packet filter function performs an imper- fect address filtering against the hash table. the imperfect filtering against the hash table is the same imperfect filtering process described in section 4.5.4.2, "hash only filtering mode" . 4.5.4.4 inverse filtering in inverse filtering, the packet filter block accepts incoming frames with a destination address not matching the perfect address (i.e., the value programmed into the mac address hig h register and the mac address low register in the crc block) and rejects frames with destination addresses matching the perfect address. for all filtering modes, when mcpas is se t, all multicast frames ar e accepted. when the prms bit is set, all frames are accepted regardless of their destination address. this includes all broadcast frames as well. 4.5.5 wakeup frame detection setting the wakeup frame enable (wuen) bit in the wakeup control and status register (wucsr) , places the mac in the wakeup frame detection mode. in this mode, normal data reception is disabled, and detection logic within the mac examines receive data for the pre-programmed wakeup fr ame patterns. when a wakeup pattern is received, the remote wakeup frame received (wufr) bit in the wucsr is set, the device pl aces itself in a fully operational state, and remote wakeup is issued. the host will then resume the device and read the wuscr register to determine the condition that caused the remote wakeup. upon determinin g that the wufr bit is set, the host will know a wakeup frame detection event was the cause. the host will then clear the wufr bit, and clear the wuen bit to resume normal receive operation. refer to section 6.4.12, "wakeup control and status register (wucsr)" for additional information on this register. before putting the mac into the wakeup frame detection state, the ho st must provide the detection logic with a list of sample frames and their corresponding by te masks. this information is written into the wakeup frame filter register (wuff). refer to section 6.4.11, "wakeup frame filter (wuff)" for additional information on this register. table 4-46 indicates the number of wakeup frame filters cont ained in the wuff.the number of writes/reads required to program the wuff or read its contents, respectively, is also indicated. the programmable filters support many di fferent receive packet patterns. if remote wakeup mode is enabled, the remote wakeup function receives all frames addressed to the ma c. it then checks each frame a gainst the enabled filter and recognizes the frame as a remote wakeup frame if it passes the wuffs address filtering and crc value match. in order to determine which bytes of the frames should be checked by the crc module, the mac uses a programmable byte mask and a programmable pattern offs et for each of the supported filters. the patterns offset defines the location of the first byte that should be checked in the frame. the byte mask is a 128- bit field that specifies whether or not ea ch of the 128 contiguous bytes within the frame, beginning in the pattern offset, should be checked. if bit j in the byte mask is set, the detection logic checks byte offset +j in the frame. in order to load the wakeup frame filter register, the host lan driver software must perf orm the number of writes indi- cated in table 4-46 to the devices wakeup frame filter register (wuf f). the contents of the wakeup frame filter reg- ister may be obtained by reading it. the number of reads r equired to extract the entire contents of the devices wuff is also indicated in table 4-46 . table 4-47 shows the wakeup frame fi lter registers structure. table 4-46: wakeup frame filter capacity number of filters number of writes/reads 84 0 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 66 ? 2012-2015 microchip technology inc. the filter i byte mask defines which incoming frame bytes f ilter i will examine to determin e whether or not this is a wakeup frame. table 4-48 , describes the byte masks bit fields. filter x mask 0 corresponds to bits [31:0]. where the lsb corresponds to the first byte on the wire. table 4-47: wakeup frame filter register structure filter 0 byte mask 0 filter 0 byte mask 1 filter 0 byte mask 2 filter 0 byte mask 3 filter 1 byte mask 0 filter 1 byte mask 1 filter 1 byte mask 2 filter 1 byte mask 3 filter 2 byte mask 0 filter 2 byte mask 1 filter 2 byte mask 2 filter 2 byte mask 3 filter 3 byte mask 0 filter 3 byte mask 1 filter 3 byte mask 2 filter 3 byte mask 3 filter 4 byte mask 0 filter 4 byte mask 1 filter 4 byte mask 2 filter 4 byte mask 3 filter 5 byte mask 0 filter 5 byte mask 1 filter 5 byte mask 2 filter 5 byte mask 3 filter 6 byte mask 0 filter 6 byte mask 1 filter 6 byte mask 2 filter 6 byte mask 3 filter 7 byte mask 0 filter 7 byte mask 1 filter 7 byte mask 2 filter 7 byte mask 3 reserved filter 3 command reserved filter 2 command reserved filter 1 command reserved filter 0 command reserved filter 7 command reserved filter 6 command reserved filter 5 command reserved filter 4 command filter 3 offset filter 2 offset filter 1offset filter 0 offset filter 7 offset filter 6 offset filter 5 offset filter 4 offset filter 1 crc-16 filter 0 crc-16 filter 3 crc-16 filter 2 crc-16 filter 5 crc-16 filter 4 crc-16 filter 7 crc-16 filter 6 crc-16 downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 67 lan9730/lan9730i filter x mask 1 corresponds to bits [63:32]. where the lsb corresponds to the first byte on the wire. filter x mask 2 corresponds to bits [95:64]. where the lsb corresponds to the first byte on the wire. filter x mask 3 corresponds to bits [127:96]. where the lsb corresponds to the first byte on the wire. the following tables define the wuff register structures. the filter i command register controls filter i operation. table 4-49 shows the filter i command register. the filter i offset register defines the offset in the frames destination address field from which the frames are examined by filter i. table 4-50 describes the filter i offset bit fields. table 4-48: filter i byte mask bit definitions filter i byte mask description bits description 127:0 byte mask: if bit j of the byte mask is set, the crc machine processes byte pattern-offset + j of the incoming frame. otherwise, byte pattern-offset + j is ignored. table 4-49: filter i command bit definitions filter i commands bits description 3:2 address type: defines the destinat ion address type of the pattern. 00 = pattern applies only to unicast frames. 10 = pattern applies only to multicast frames. x1 = pattern applies to all frames that have passed the regular receive filter. 1 reserved 0 enable filter: when bit is set, filter i is enabled, otherwise, filter i is disabled. table 4-50: filter i o ffset bit definitions filter i offset description bits description 7:0 pattern offset: the offset of the first byte in the fr ame on which crc is checked for wakeup frame recognition. the mac checks the first offset byte of the frame for crc and checks to determine whether the frame is a wakeup frame. offset 0 is the first byte of the in coming frame's destination address. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 68 ? 2012-2015 microchip technology inc. the filter i crc-16 register contains the crc-16 result of the frame that should pass filter i. table 4-51 describes the filter i crc-16 bit fields. table 4-52 indicates the cases that produce a wake when the wakeup frame enable (wuen) bit of the wakeup control and status register (wucsr) is set. all other cases do not generate a wake. note 4-20 as determined by bit 0 of filter i command. note 4-21 crc matches filter i crc-16 field. note 4-22 as determined by bit 9 of wucsr. note 4-23 as determined by bits 3: 2 of filter i command. note 4-24 when wakeup frame detection is enabled via the wakeup frame enable (wuen) bit of the wakeup control and status register (wucsr) , a broadcast wakeup frame will wake up the device despite the state of the disable broadcast frames (bcast) bit in the mac control register (mac_cr) . table 4-51: filter i crc-16 bit definitions filter i crc-16 description bits description 15:0 pattern crc-16: this field contains the 16-bit crc value from the pattern and the byte mask pro- grammed to the wakeup filter register function. this value is compared against the crc calculated on the incoming frame, and a match i ndicates the reception of a wakeup frame. table 4-52: wakeup generation cases filter enabled ( note 4-20 ) crc match ( note 4-21 ) global unicast enabled ( note 4-22 ) pass regular receive filter address type ( note 4-23 ) broad- cast frame ( note 4-24 ) multicast frame unicast frame yes yes x x x yes no no yes yes yes x x no no yes yes yes x yes multicast (=10) no yes no yes yes x yes unicast (=00) no no yes y e sy e sxy e sp a s s e d receive filter (=x1b) xxx note: x indicates dont care. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 69 lan9730/lan9730i 4.5.6 magic packet detection setting the magic packet enable (mpen) bit in the wakeup control and status register (wucsr) , places the mac in the magic packet detection mode. in this mode, normal data reception is disabled, and detection logic within the mac examines receive data for a magic packet. when a magic packet is received, the magic packet received (mpr) bit in the wucsr is set, the device places itself in a fully operat ional state, and remote wake up is issued. the host will then resume the device and read the wuscr register to determine the condition t hat caused the remote wakeup. upon determining that the mpr bit is set, the host will know recept ion of a magic packet was the cause. the host will then clear the mpr bit, and clear the mpen bit to resume normal receive operation. refer to section 6.4.12, "wakeup control and status register (wucsr)" for additional information on this register. in magic packet mode, the power management logic const antly monitors each frame addressed to the node for a spe- cific magic packet pattern. it checks on ly packets with the macs address or a broadcast address to meet the magic packet requirement. the power management logic checks each received frame for the pattern 48h ff_ff_ff_ff_ff_ff after the destination and source address field. then the function looks in the frame for 16 repetitions of t he mac address without any breaks or interruptions. in case of a break in the 16 address repetitions , the pmt function scans for the 48'h ff_ff_ff_ff_ff_ff pattern again in the incoming frame. the 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. the device will also accept a multicast frame, as long as it detects the 16 duplications of the mac address. if the mac address of a node is 00h 11h 22h 33h 44h 55h, then the mac scans fo r the following data sequence in an ethernet frame: destination address source ad dress ff ff ff ff ff ff 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 crc 4.5.7 receive checksum offload engine (rxcoe) the receive checksum offload engine provides assistance to the host by calculating a 16-bit checksum for a received ethernet frame. the rxcoe readily suppo rts the following ieee 802.3 frame formats: type ii ethernet frames snap encapsulated frames support for up to 2, 802.1q vlan tags the resulting checksum value can also be modified by software to support other frame formats. the rxcoe has two m odes of operation. in mode 0, the rxcoe calculates the che cksum between the first 14 bytes of the ethernet frame and the fc s. this is illustrated in figure 4-10 . figure 4-10: rxcoe checksum calculation dst src ty p e frame data f cs calculate checksum downloaded from: http:///
lan9730/lan9730i ds00001946a-page 70 ? 2012-2015 microchip technology inc. in mode 1, the rxcoe supports vlan tags and a snap header. in this mode, the rxcoe calculates the checksum at the start of l3 packet. the vlan1 tag register is used by th e rxcoe to indicate what protocol type is to be used to indicate the existence of a vlan t ag. this value is typically 8100h. example frame configurations: figure 4-11: type ii ethernet frame figure 4-12: ethernet frame with vlan tag figure 4-13: ethernet frame with length field and snap header dst src pr o t 0 1 2 3 l3 packet f c s calculate checksum 1dword dst src 81 0 0 vi d 0 1 2 3 ty p e 4 l3 packet f c s calculate checksum 1dword dst src l3 packet fc s sn a p 0 sn a p 1 le n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 3 4 5 calculate checksum 1dword downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 71 lan9730/lan9730i the rxcoe supports a maximum of two vlan tags. if there ar e more than two vlan tags, the vlan protocol identifier for the third tag is treated as an ethernet type field. the ch ecksum calculation will begin immediately after the type field. the rxcoe resides in the rx path within the mac. as the rxcoe receives an ethernet fram e, it calculates the 16-bit checksum. the rxcoe passes the ethernet frame to the rx fifo with the checksum appended to the end of the frame. the rxcoe inserts the checksum immediately after the last by te of the ethernet frame and before it transmits the status word. the packet length field in the rx status word (refer to section 4.4.1.2 ) will indicate that the frame size has increased by two bytes to accommodate the checksum. setting the rxcoe_en bit in the checksum offload engine co ntrol register (coe_cr) enables the rxcoe, while the rxcoe_mode bit selects the operating mode. when the rxcoe is disabled, the received data is simply passed through the rxcoe unmodified. figure 4-14: ethernet frame with vlan tag and snap header figure 4-15: ethernet frame with multiple vlan tags and snap header note: when enabled, t he rxcoe calculates a checksum for every received frame. note: software applications must stop the receiver and flus h the rx data path before changing the state of the rxcoe_en or rxcoe_mode bits. note: when the rxcoe is enabled, automat ic pad stripping must be disabled (bit 8 (padstr) of the mac con- trol register (mac_cr) ) and vice versa. these functions cannot be enabled simultaneously. dst src 81 0 0 vi d l3 packet f c s sn a p 0 sn a p 1 3 le n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 4 5 6 calculate checksum 1dword dst src 81 0 0 vi d l3 packet fc s sn a p 0 sn a p 1 5 le n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 6 7 8 calculate checksum 81 0 0 vi d 4 1dword downloaded from: http:///
lan9730/lan9730i ds00001946a-page 72 ? 2012-2015 microchip technology inc. 4.5.7.1 rx checksum calculation the checksum is calculated 16 bits at a time. in the case of an odd sized frame, an extra byte of zero is used to pad up to 16 bits. consider the following packet: da, sa, type, b0, b1, b2 bn, fcs let [a, b] = a*256 + b if the packet has an even number of octets then checksum = [b1, b0] + c0 + [b3, b2] + c1 + + [bn, bn-1] + cn-1 where c0, c1, ... cn-1 are the carry out results of the intermediate sums. if the packet has an odd number of octets then checksum = [b1, b0] + c0 + [b3, b2] + c1 + + [0, bn] + cn-1 4.5.8 transmit checksum offload engine (txcoe) the transmit checksum offload engine provides assistance to the cpu by calculating a 16- bit checksum, typically for tcp, for a transmit ethernet frame. the txcoe calculates the checksum and inserts the re sults back into the data stream as it is transferred to the mac. to activate the txco e and perform a checksum calculati on, the host must first set the tx checksum offload engine enable (tx_coe_en) bit in the checksum offload engine co ntrol register (coe_cr) . the host then pre-pends a 3 dword buffer to the data that will be transmitted. the pre-pended buffer includes a tx command a, tx command b, and a 32-bit tx checksu m preamble (refer to table 4-53 ). when the ck bit of the tx command b is set in conjunction with the fs bit of tx command a and the tx_coe_en bi t of the coe_cr register, the txcoe will perform a check- sum calculation on the associated packet. the tx checksum preamble instructs the txcoe on the handling of the asso- ciated packet. the txcssp - tx checksum start pointer field of the tx checksum preamb le defines the byte offset at which the data checksum calculation will be gin. the checksum calculation will begin at this offset and will continue until the end of the packet. the data checksum calculation must not begin in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. when the calculation is complete, the checksum will be inserted into the packet at the byte offset defined by the txcsloc - tx checksum location field of the tx checksum preambl e. the tx checksum cannot be inserted in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. if the ck bit is not set in the first tx command b of a packet, the packet is passed directly th rough the txcoe without modi fication, regardless if the txcoe_en is set. an example of a tx packet with a pre-pended tx checksum preamble can be found in section 4.4.2.9, "tx example 3" . in this example, the host pr ovides the ethernet frame to the ethernet controller (via a usb packet) in four fragments, the first containing the tx checksum preamble. figure 4-8 shows how these fragments are loaded into the tx data fifo. for more information on the tx command a and tx command b, refer to section 4.4.2.1, "tx command format" . if the tx packet already includes a partial checksum calc ulation (perhaps inserted by an upper layer protocol), this checksum can be included in the hardware checksum calculation by setting the tx cssp field in the tx checksum pre- amble to include the partial checksum. the partial checksum can be replac ed by the completed ch ecksum calculation by setting the txcsloc pointer to point to the location of the partial checksum. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 73 lan9730/lan9730i table 4-53: tx checksum preamble field description 31:28 reserved 27:16 txcsloc - tx checksum location this field specifies the byte offset where the tx checksum will be inserted in the tx packet. the checksum will replace two bytes of data starting at this offset. note: the tx checksum cannot be inserted in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. 15:12 reserved 11:0 txcssp - tx checksum start pointer this field indicates start offset, in bytes, where the checksum calculation will begin in the associated tx packet. note: the data checksum calculation must not begin in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. note: when the txcoe is enabled, the third dword of the pre-pended packet is not transmitted. however, 4 bytes must be added to the packet length field in tx command b. note: software applications must stop the transmitter and flus h the tx data path before changing the state of the txcoe_en bit. however, the ck bit of tx command b can be set or cleared on a per-packet basis. note: the txcoe_mode may only be changed if the tx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the tx ethernet path is disabl ed and the tli is empty. note: the tx checksum preamble must be dword-aligned. note: tx preamble size is accounted for in both the buffer length and packet length. note: the first buffer, which contains the tx prea mble, may not contain any ethernet frame data. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 74 ? 2012-2015 microchip technology inc. figure 4-16 illustrates the use of a pre-pended checksum preambl e when transmitting an ethernet frame consisting of 3 payload buffers. figure 4-16: tx example illustratin g a pre-pended tx checksum preamble tx command 'a' pad dword 1 tx command 'a' tx command 'b' 10-byte end offset padding payload fragment 2 tx command 'a' tx command 'b' data written to the device payload fragment 3 tx command 'a' tx command 'b' tx checksum preamble note: the tx checksum preamble is pre-pended to data to be transmitted. fs is set in tx command 'a' and ck is set in tx command 'b'. no start offset may be added. fs must not be set for subsequent fragments of the same packet. tx command 'b' payload fragment 1 downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 75 lan9730/lan9730i 4.5.8.1 tx checksum calculation the tx checksum calculation is performed using the same operatio n as the rx checksum shown in section 4.5.7.1 , with the exception that the calculation starts as i ndicated by the preamble , and the transmitted checksum is the ones- compliment of the final calculation. 4.5.9 mac control and status registers (mcsr) refer to section 6.4, "mac control and status registers" for a complete descr iption of the mcsr. 4.6 10/100 internal ethernet phy the device integrates an ieee 802.3 physical layer for twis ted pair ethernet applications. the phy can be configured for either 100 mbps (100base-tx) or 10 mbps (10base-t) ethernet o peration in either full- or half-duplex configura- tions. the phy block includes auto-negotiation. minimal exter nal components are required for the utilization of the inter- nal phy. the device provides an option to use an external phy in place of the internal phy. the external phy can be connected via the media independent interface (mii) port. this opti on is useful for supporting home pna operations. when an external phy is used, the internal phy must be placed into general power down via a phy reset (refer to section 4.6.9, "phy resets" for further information). functionally, the internal phy can be divided into the following sections: 100base-tx transmit and receive 10base-t transmit and receive internal mii to the ethernet media access controller auto-negotiation to automat ically determine the best speed and duplex possible management control to read status re gisters and write control registers the devices ethernet interface requires a software sequ ence to be compli ant with the ieee 802.3 output v oh+ /v oh- voltage specification. microchip has no t experienced any functional limitations if this sequence is not implemented, although ieee 802.3 compliance may fail by approximately 25 mv if not enabled. the software sequence has been implemented successfully in the driver released by microchi p. refer to the microchip driver source code for an example of this implementation. the following pseudo-code structur es detail the required sequence: // enable access to voh compliance registers reg_access_enable: mii_write: address 0x14, data 0x0400 mii_write: address 0x14, data 0x0000 mii_write: address 0x14, data 0x0400 // enable the voh compliance mode phy_vohcomp_enable: mii_write: address 0x17, data 0x85e8 (read mii address 0x14 until bit 14 is cleared) mii_write: address 0x14, data 0x4416 note: when the tx checksum offload feature is invoked, if the calculated checksum is 0000h, it is left unaltered. udp checksums are optional under ipv4, and a zero checksum calcul ated by the tx checksum offload feature will erroneously indicate to the receiver that no checksum was calculated, however, the packet will typically not be rejected by the receiver. under ip v6, however, according to rfc 2460, the udp checksum is not optional. a calculated checksu m that yields a result of zero mu st be changed to ff ffh for insertion into the udp header. ipv6 receivers discard udp packets containing a zero checksum. thus, this feature must not be used for udp checksum calculation under ipv6. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 76 ? 2012-2015 microchip technology inc. // check that the voh compliance mode is active phy_vohcomp_check: mii_write: address 0x14, data 0x86c0 (read mii address 0x14 until bit 15 is cleared) mii_read: address 0x15 (if readdata = 16'bxxxxxx11xxxxxxxx, th en voh compliance is enabled) the entire sequence that should occur is: reg_access_enable -> phy_vohcom p_enable -> phy_vohcomp_check it is recommended to run this sequence upon the followi ng list of events detected by the software driver: 1. device hardware reset: a) assertion of the external chip reset (nreset) b) power on reset (por) 2. device software reset: a) setting of the soft reset (srst) bit of the hardware configuration register (hw_cfg) b) setting of the phy soft reset bit of the basic control register 3. exit from energy detect power-down (edpd) mode 4. auto-negotiation enable/disable via the auto-negotiation enable bit of the basic control register 5. exit from general power-down mode 4.6.1 100base-tx transmit the data path of the 100base-tx is shown in figure 4-17 . each major block is explained in the following sections. figure 4-17: 100base-tx data path mac tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 100m pll internal mii 25 mhz by 4 bits tx_clk 25 mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii 25 mhz by 4 bits downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 77 lan9730/lan9730i 4.6.1.1 4b/5b encoding the transmit data passes from the mii block to the 4b/5b enc oder. this block encodes the data from 4-bit nibbles to 5- bit symbols (known as code-groups) according to table 4-54 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slashe s on either side. for example, an idle code-group is / i/, a transmit error code-group is /h/, etc. the encoding process may be bypassed by clearing bit 6 of register 31. when the encoding is bypassed, the 5 th transmit data bit is equivalent to tx_er. table 4-54: 4b/5b code table code group sym receiver interpreta tion transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 i idle sent after /t/r until tx_en 11000 j first nibble of ssd, translated to 0101 following idle, else rx_er sent for rising tx_en 10001 k second nibble of ssd, translated to 0101 following j, else rx_er sent for rising tx_en 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of rx_er sent for falling tx_en 00111 r second nibble of esd, causes deasser- tion of crs if following /t/, else assertion of rx_er sent for falling tx_en 00100 h transmit error symbol sent for rising tx_er 00110 v invalid, rx_er if during rx_dv invalid 11001 v invalid, rx_er if during rx_dv invalid 00000 v invalid, rx_er if during rx_dv invalid 00001 v invalid, rx_er if during rx_dv invalid 00010 v invalid, rx_er if during rx_dv invalid 00011 v invalid, rx_er if during rx_dv invalid 00101 v invalid, rx_er if during rx_dv invalid 01000 v invalid, rx_er if during rx_dv invalid 01100 v invalid, rx_er if during rx_dv invalid downloaded from: http:///
lan9730/lan9730i ds00001946a-page 78 ? 2012-2015 microchip technology inc. 4.6.1.2 scrambling repeated data patterns (especially the idle code-group) ca n have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi from being radiated by the physical wiring. the scrambler also performs the parallel in serial out conversion (piso) of the data. 4.6.1.3 nrzi and mlt-3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125 mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt-3 is a tri- level code where a change in the logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit 0. 4.6.1.4 100m transmit driver the mlt-3 data is then passed to the analog transmitter, which launches the differential mlt-3 signal, on outputs txp and txn, to the twisted pair media via a 1:1 ratio isolat ion transformer. the 10base-t and 100base-tx signals pass through the same transformer so that common magnetics can be used for both. the transmitter drives into the 100 ? impedance of the cat-5 cable. cable termination a nd impedance matching require external components. 4.6.1.5 100m phase lock loop (pll) the 100m pll locks onto reference clock and generates the 125 mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 4.6.2 100base-tx receive the receive data path is shown in figure 4-18 . detailed descriptions are given in the following subsections. 10000 v invalid, rx_er if during rx_dv invalid figure 4-18: receive data path table 4-54: 4b/5b code table (continued) code group sym receiver interpretation transmitter interpretation mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll internal mii 25 mhz by 4 bits rx_clk 25 mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii 25 mhz by 4 bits downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 79 lan9730/lan9730i 4.6.2.1 100m receive input the mlt-3 from the cable is fed into the phy (on inputs rxp and rxn) via a 1:1 ratio transformer. the adc samples the incoming differential signal at a rate of 125m samples per second. using a 64-level quant izer, it generates 6 digital bits to represent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such that the full dynamic range of the adc can be used. 4.6.2.2 equalizer, baseline wander correction and clock and data recovery the 6 bits from the adc are fed into the dsp block. the equalizer in the dsp section compensates for phase and ampli- tude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-quality cat-5 cable between 1 m and 150 m. if the dc content of t he signal is such that the low-frequency comp onents fall below the low frequency pole of the iso- lation transformer, then the droop characteristics of the transformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the phy corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined killer packet with no bit errors. the 100m pll generates multiple phases of the 125 mhz clock. a multiplexer, controlled by the timing unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clock. this clock is used to extract the serial data from the received signal. 4.6.2.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered le vels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. 4.6.2.4 descrambling the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols, the descrambler synchronizes its descram bler key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization with the remote phy by searching for idle symbols within a window of 4000 bytes (40 s). this window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802.3 standard, can be received with no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process. the descrambler can be bypassed by setting bit 0 of register 31. 4.6.2.5 alignment the de-scrambled signal is then aligned into 5-bit code-grou ps by recognizing the /j/k/ st art-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 4.6.2.6 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibbles according to the 4b/5b table. the ssd, /j/k/, is translated to 0101 0101 as the first 2 nibbles of the mac preamble. re ception of the ssd causes the phy to assert the internal rx_dv signal, indicating that valid data is available on t he internal rxd bus. successive valid code-groups are trans- lated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t/r/ symbols, or at least two /i/ symbols causes the phy to de-assert the internal carrier sense and rx_dv. these symbols are not translated into data. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 80 ? 2012-2015 microchip technology inc. 4.6.2.7 receiver errors during a frame, unexpected code-groups are considered re ceive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the internal miis rx_er signal is asserted and arbitrary data is driven onto the internal receive data bu s (rxd) to the mac. should an error be detected during the time that the /j/k/ delimiter is being decoded (bad ssd e rror), rx_er is asserted and the value 1110b is driven onto the internal receive data bus (rxd) to the mac. note that the internal miis data valid signal (rx_dv) is not yet asserted when the bad ssd occurs. 4.6.3 10base-t transmit data to be transmitted comes from the mac layer controller . the 10base-t transmitter receives 4-bit nibbles from the mii at a rate of 2.5 mhz and converts them to a 10 mbps serial data stream. the data stream is then manchester encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. the 10m transmitter uses the following blocks: mii (digital) tx 10m (digital) 10m transmitter (analog) 10m pll (analog) 4.6.3.1 10m transmit data across the internal mii bus the mac controller drives the transmit data onto the internal txd bus. when the controller has driven tx_en high to indicate valid data, the data is latched by the mii block on the rising edge of tx_clk. the data is in the form of 4-bit wide 2.5 mhz data. 4.6.3.2 manchester encoding the 4-bit wide data is sent to the tx10m block. the nibbles are converted to a 10 mbps se rial nrzi data stream. the 10m pll locks onto the external clock or internal oscillato r and produces a 20 mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (tx_en is low), the tx10m block outputs normal link pulses (nlps) to maintain communications with the remote link partner. 4.6.3.3 10m transmit drivers the manchester encoded data is sent to the analog tran smitter where it is shaped a nd filtered before being driven out as a differential signal acro ss the txp and txn outputs. 4.6.4 10base-t receive the 10base-t receiver gets the manchester encoded analog signal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller across the mii at a rate of 2.5 mhz. this 10m receiver uses the following blocks: filter and squelch (analog) 10m pll (analog) rx 10m (digital) mii (digital) downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 81 lan9730/lan9730i 4.6.4.1 10m receive input and squelch the manchester signal from the cable is fed into the phy (on inputs rxp and rxn) via 1:1 ratio magnetics. it is first filtered to reduce any out-of-band noise. it then passes through a squelch circuit. the squelch is a set of amplitude and timing comparators that normally reject differential vo ltage levels below 300 mv and detect and recognize differen- tial voltages above 585 mv. 4.6.4.2 manchester decoding the output of the squelch goes to the rx10m block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the pol arity is reversed (local rxp is connect ed to rxn of the remote partner and vice versa), then this is identified and corrected. the reversed cond ition is indicated by the flag xpol, bit 4 in register 27. the 10m pll is locked onto the received manchester signal and from this, generates the received 20 mhz clock. using this clock, the manchester encoded data is extracted and converted to a 10 mhz nrz i data stream. it is then converted from serial to 4-bit wide parallel data. the rx10m block also detects valid 10ba se-t idle signals - normal link pulses (nlps) - to maintain the link. 4.6.4.3 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, that results in holding the tx_en input for a long period. special logic is used to detect the jabber state and abort the transmission to the line, within 45 ms. once tx_en is deasserted, the logic resets the jabber condition. 4.6.5 auto-negotiation the purpose of the auto-n egotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its link partner. auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically sele cting the highest performance mode of ope ration supported by both sides. auto- negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal serial management interface (smi). the results of the negotiation process are reflected in the speed indication bits in register 31, as well as the link partner ability register (register 5). the auto-negotiation protocol is a purely physical layer activity and proceeds independently of the mac controller. the advertised capabilities of the phy ar e stored in register 4 of the smi registers. the defau lt advertised by the phy is determined by user-defined on-chip signal options. the following blocks are activated during an auto-negotiation session: auto-negotiation (digital) 100m adc (analog) 100m pll (analog) 100m equalizer/blw/clock recovery (dsp) 10m squelch (analog) 10m pll (analog) 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of one of the following events: hardware reset software reset power-down reset link status down setting register 0, bit 9 hi gh (auto-negotiation restart) downloaded from: http:///
lan9730/lan9730i ds00001946a-page 82 ? 2012-2015 microchip technology inc. on detection of one of these events, the phy begins auto-negotiation by tran smitting bursts of fast link pulses (flp). these are bursts of link pulses from the 10m transmitter. they are shaped as normal link pulses and can pass uncor- rupted down cat-3 or cat-5 cable. a fa st link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, frame the flp burst. the 16 even- numbered pulses, which may be present or absent, contain the data word being transmitted. presence of a data pu lse represents a 1, while absence represents a 0. the data transmitted by an flp burst is known as a link c ode word. these are defined fu lly in ieee 802.3 clause 28. in summary, the phy advertises 802.3 compliance in its selector field (the first 5 bits of the link code word). it adver- tises its technology ability according to the bits set in register 4 of the smi registers. there are 4 possible matches of the technology abilities. in the order of priority these are: 100m full-duplex (highest priority) 100m half-duplex 10m full-duplex 10m half-duplex if the full capabilities of the phy are adv ertised (100m, full-duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 100m as th e highest performance mode. if the link partner is capable of half- and full- duplex modes, then auto-negotiation selects full -duplex as the highest performance operation. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif- ference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. writing register 4 bits [8:5] allows software control of the capabilities advertised by the ph y. writing register 4 does not automatically re-start auto-negotiation. register 0, bit 9 must be set before th e new abilities will be advertised. auto- negotiation can also be disabled via software by clearing register 0, bit 12. the device does not support next page capability. 4.6.6 parallel detection if lan9730/lan9730i is connected to a device lacking the ability to auto-negotiate (i .e., no flps are detected), it is able to determine the speed of the link based on either 100m mlt- 3 symbols or 10m normal link pulses. in this case the link is presumed to be ha lf-duplex per the ieee st andard. this ability is known as parallel detection. this feature ensures interoperability with legacy link part ners. if a link is formed via parallel det ection, then bit 0 in register 6 is cle ared to indicate that the link partner is not capable of auto- negotiation. the ethernet mac has access to this information via the management interface. if a fault occurs during parallel detection, bit 4 of register 6 is set. register 5 is used to store the link partner ability informat ion, which is coded in the received flps. if the link partner is not auto-negotiation capable, then regist er 5 is updated after completion of parallel detection to reflect the speed capa- bility of the link partner. 4.6.6.1 re-starting auto-negotiation auto-negotiation can be re-started at any time by setting register 0, bit 9. auto-negotiation will also re-start if the link is broken at any time. a broken link is ca used by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation resumes in an attempt to determine the new link configuration. if the management entity re-starts auto-negotiation by writing to bit 9 of the control register, the device will respond by stopping all transmission/receiving operations. once the br eak_link_timer is done, in the auto-negotiation state-machine (approximately 1250 ms) the auto-negotiation will re-start. th e link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. 4.6.6.2 disabling auto-negotiation auto-negotiation can be disabled by setting register 0, bi t 12 to zero. the device will then force its speed of operation to reflect the information in register 0, bit 13 (speed) and re gister 0, bit 8 (duplex). the speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 83 lan9730/lan9730i 4.6.6.3 half vs. full-duplex half-duplex operation relies on the csma/ cd (carrier sense multiple access/collision detect) protocol to handle net- work traffic and collisions. in this mode, the internal carri er sense signal, crs, responds to both transmit and receive activity. in this mode, if data is received while the phy is transmitting, a collision results. in full-duplex mode, the phy is able to transmit and receive data simultaneously. in this mode, the internal crs responds only to receive activity. the csma/cd protocol does not apply and collision detection is disabled. table 4-55 describes the behavior of the internal crs bit under all receive/transmit conditions. the internal crs signal is used to trigger bit 10 (no carrier) of the tx status word (see section 4.4.2.6, "tx status format" ). the crs value, and subsequently the no carrier val ue, are invalid during any full- duplex transmission. there- fore, these signals cannot be used as a verification me thod of transmitted packets when transmitting in 10/100 mbps full-duplex modes. note 4-25 the devices 10/100 phy internal crs signal operates in two modes: active and low. when in active mode, the internal crs will transition high and low upon line activity, where a high value indicates a carrier has been detected. in low mode, the internal crs stays low and does not indicate carrier detection. the internal crs signal and no carrier (bit 10 of the tx status word) cannot be used as a verification method of transmitted packets wh en transmitting in 10/100 mbps full-duplex mode. table 4-55: crs behavior mode speed duplex activity crs behavior note 4-25 manual 10 mbps half-duplex transmitting active manual 10 mbps half-duplex receiving active manual 10 mbps full-duplex transmitting low manual 10 mbps full-duplex receiving active manual 100 mbps half-duplex transmitting active manual 100 mbps half-duplex receiving active manual 100 mbps full-duplex transmitting low manual 100 mbps full-duplex receiving active auto-negotiation 10 mbps half-duplex transmitting active auto-negotiation 10 mbps half-duplex receiving active auto-negotiation 10 mbps full-duplex transmitting low auto-negotiation 10 mbps full-duplex receiving active auto-negotiation 100 mbps half-duplex transmitting active auto-negotiation 100 mbps half-duplex receiving active auto-negotiation 100 mbps full-duplex transmitting low auto-negotiation 100 mbps full-duplex receiving active downloaded from: http:///
lan9730/lan9730i ds00001946a-page 84 ? 2012-2015 microchip technology inc. 4.6.7 hp auto-mdix hp auto-mdix facilitates the use of cat-3 (10base-t) or cat-5 (100base-tx) media utp interconnect cable without consideration of interface wiri ng scheme. if a user plugs in either a direct connect lan cable, or a cross-over patch cable, as shown in figure 4-19 , the devices auto-mdix phy is capable of configuring the tpo and tpi twisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pi ns of the connecting device. since the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function can be disabled through the special control/status indications register or the external automdix_en configuration strap. note: when operating in 10base-t or 100base-tx manual modes, the auto-mdix crossover time can be extended via the extend manual 10/100 auto-mdix crossover time bit of the edpd nlp/crossover tim- eregister . refer to section 6.5.8, "edpd nlp/ crossover timeregister" for additional information. figure 4-19: direct cable connection vs. cross-over cable connection 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 85 lan9730/lan9730i 4.6.8 phy power-down modes there are two power-down modes for the phy as discussed in the following sections. 4.6.8.1 general power-down this power-down is controlled by register 0, bit 11. in th is mode the phy, except the ma nagement interface, is powered- down and stays in that condition as long as phy register bit 0.11 is high. when bit 0.11 is cleared, the phy powers up and is automatically reset. refer to section 6.5.1, "basic control register" for additional information on this register. 4.6.8.2 energy detect power-down (edpd) this power-down mode is activated by setting the edpwrdown bit of the mode control/status register . in this mode, when no energy is present on the line, the phy is power ed down (except the one for the management interface, the squelch circuit, and the energyon l ogic). the energyon logic is used to detect the presence of valid energy from 100base-tx, 10base-t, or auto-negotiation signals. in this mode, when the energyon bit of the mode control/status register is low, the phy is powered-down and noth- ing is transmitted. when energy is received via link pulses or packets, the energyon bit goes high and the phy pow- ers-up. the phy automatically re sets itself into the state prior to power-down and asserts the int7 bit of the phy interrupt source flag register register. if the energyon interrupt is enabled, this event will cause a phy interrupt to the interrupt controller and the power management event det ection logic. the first and possibly the second packet to activate energyon may be lost. when the edpwrdown bit of the mode control/status register is low, energy detect power-down is disabled. when in edpd mode, the devices nlp characteristics may be modified. the device can be configured to transmit nlps in edpd via the edpd tx nlp enable bit of the edpd nlp/crossover timeregister . when enabled, the tx nlp time interval is configurable via the edpd tx nlp interval timer select field of the edpd nlp/crosso ver timeregister . when in edpd mode, the device can also be configured to wake on the reception of one or two nlps. setting the edpd rx single nlp wake enable bit of the edpd nlp/crosso ver timeregister will enable the device to wake on reception of a single nlp. if the edpd rx single nlp wake enable bit is cleared, the maximum in terval for detecting reception of two nlps to wake from edpd is configurable via the edpd rx nlp max interval detect select field of the edpd nlp/crossover timeregister . 4.6.9 phy resets in addition to a chip-level reset, the phy supports two software-initiated resets. these are discussed in the following sections. 4.6.9.1 phy soft reset via pmt_ctl register phy reset (phy_rst) bit the phy soft reset is initiated by writing a 1 to the phy reset (phy_rst) bit of the power management control reg- ister (pmt_ctl) . this self-clearing bit will return to 0 after appr oximately 2 ms, at which time the phy reset is com- plete. 4.6.9.2 phy soft reset via phy basic c ontrol register bit 15 (phy reg. 0.15) the phy reg. 0.15 soft reset is initiated by writing a 1 to bit 15 of the phys basic contro l register. this self-clearing bit will return to 0 after approximately 256 s, at which time the phy reset is complete. the bcr reset initializes the logic within the phy, with the exception of register bits marked as nasr (not affected by software reset). 4.6.10 required ethernet magnetics the magnetics selected for use with the device should be an auto-mdix style magnetic available from several vendors. the user is urged to review microchip application note 8.13, suggested magnetics for the latest qualified and suggested magnetics. vendors and part numbers are provided in this application note. 4.6.11 phy registers refer to section 6.5, "phy registers" for a complete description of the phy registers. note: for maximum power savings, auto-negotiation should be disabled before enabling the general power- down mode. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 86 ? 2012-2015 microchip technology inc. 4.7 eeprom controller (epc) the device may use an external eeprom to store the default values for the usb descriptors and the mac address. the eeprom controller supports most 256/512 byte 93c46 type eeproms. the mac address is used as the default ethernet mac addr ess and is loaded into the macs addrh and addrl reg- isters. if a properly configured eeprom is not detected, it is the responsibility of the host lan driver to set the ieee addresses. after a system-level reset occurs, the device will load th e default values from a properly configured eeprom. the device will not accept usb transactions from the host until this process is completed. the eeprom controller also allows the host system to re ad, write and erase the contents of the serial eeprom. 4.7.1 eeprom format table 4-56 illustrates the format in which data is stored inside of the eeprom. note the eeprom offsets are given in units of 16-bit word of fsets. a length field with a value of zero indicates that the field does not exist in the eeprom. the device will use the fiel ds hw default valu e in this case. note: a 3-wire style 2k/4k eeprom that is organize d for 256/512 x 8-bit operation must be used. note: for the device descriptor, the only valid values for the length are 0 and 18. note: for the configuration and interface descriptor, the only valid values for the length are 0 and 18. note: the eeprom programmer must ensure that if a string descriptor does not exist in the eeprom, the ref- erencing descriptor must contain 00h for the respective string index field. note: if all string descriptor lengths are zero, then a language id will not be supported. table 4-56: eeprom format eeprom address eeprom contents 00h 0xa5 01h mac address [7:0] 02h mac address [15:8] 03h mac address [23:16] 04h mac address [31:24] 05h mac address [39:32] 06h mac address [47:40] 07h full-speed polling interval for interrupt endpoint 08h hi-speed polling interval for interrupt endpoint 09h configuration flags 0ah language id descriptor [7:0] 0bh language id descriptor [15:8] 0ch manufacturer id string descriptor length (bytes) 0dh manufacturer id string de scriptor eeprom word offset 0eh product name string descriptor length (bytes) 0fh product name string descriptor eeprom word offset 10h serial number string descriptor length (bytes) 11h serial number string de scriptor eeprom word offset 12h configuration string descriptor length (bytes) 13h configuration string descriptor word offset 14h interface string descriptor length (bytes) 15h interface string descriptor word offset downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 87 lan9730/lan9730i table 4-57 describes the configuration flags. the configuration flags override the affects of the rmt_wkp strap. if a configuration descriptor exists in t he eeprom it will override both the configurat ion flags and as sociated straps. 16h hi-speed device descriptor length (bytes) 17h hi-speed device descriptor word offset 18h hi-speed configuration and in terface descriptor length (bytes) 19h hi-speed configuration and interface descriptor word offset 1ah full-speed device descriptor length (bytes) 1bh full-speed device descriptor word offset 1ch full-speed configuration and interface descriptor length (bytes) 1dh full-speed configuration and interface descriptor word offset 1eh lsb of gpio wake 0-10 (gpiowkn) field of general purpose io wake enable and polarity register (gpio_wake) 1fh msb of gpio wake 0-10 (gpiowkn) field of general purpose io wake enable and polarity register (gpio_wake) 20h gpio pme flags note: the descriptor type for the device descriptors specified in the eeprom is a don't care and always over- written by hw to 0x1. the descriptor size for the device descriptors specified in the eeprom is a don' t care and always over- written by hw to 0x12. the descriptor type for the configuration descriptors specified in the eeprom is a don't care and always overwritten by hw to 0x2. note: descriptors specified in eeprom having bcdusb, bmaxpacketsize0, and bnumconfig urations fields defined with values other than 0200h , 40h, and 1, respectively, will re sult in unwanted behavior and untow- ard results. note: eeprom byte addresses past 20h can be used to store data for any purpose. table 4-57: configuration flags bits description 7:4 reserved 3 reserved 2 remote wakeup support 0 = the device does not support remote wakeup. 1 = the device supports remote wakeup. 1 led select refer to the led select (led_sel) bit of the led general purpose io confi guration register (led_gpi- o_cfg) for bit functi on definitions. 0 power method 0 = the device is bus powered. 1 = the device is self powered. table 4-56: eeprom fo rmat (continued) eeprom address eeprom contents downloaded from: http:///
lan9730/lan9730i ds00001946a-page 88 ? 2012-2015 microchip technology inc. table 4-58 describes the gpio pme flags. table 4-58: gpio pme flags bits description 7 gpio pme enable setting this bit enables the assertion of the gpio0 or gpio8 pin, as a result of a wakeup (gpio) pin, magic packet, or phy link up. the host processo r may use the gpio0/gpio8 pin to asynchronously wake up, in a manner analogous to a pci pme pin. gpio0 signals the event when operating in internal phy mode, while gpio8 signals the event when operating in external phy mode. internal or external phy mode of operation is dictated by the phy_sel pin. 0 = the device does not support gpio pme signaling. 1 = the device supports gpio pme signaling. note: when this bit is 0, the remaining gpio pme parameters in this flag byte are ignored. 6 gpio pme configuration this bit selects whether the gpio pme is signaled on the gpio pin as a level or a pulse. if pulse is selected, the duration of the pulse is determined by the setting of the gpio pme length bit of this flag byte. the level of the signal or the polarity of the pulse is determined by the gpio pme polarity bit of this flag byte. 0 = gpio pme is signaled via a level. 1 = gpio pme is signaled via a pulse. note: if gpio pme enable is 0, this bit is ignored. 5 gpio pme length when the gpio pme configuration bit of this flag byte indicates that the gpio pme is signaled by a pulse on the gpio pin, this bit determines the duration of the pulse. 0 = gpio pme pulse length is 1.5 ms. 1 = gpio pme pulse length is 150 ms. note: if gpio pme enable is 0, this bit is ignored. 4 gpio pme polarity specifies the level of the signal or the polarity of the pulse used for gpio pme signaling. 0 = gpio pme signaling polarity is low. 1 = gpio pme signaling polarity is high. note: if gpio pme enable is 0, this bit is ignored. 3 gpio pme buffer type this bit selects the output buffer type for gpio0/gpio8. 0 = open drain driver/open source 1 = push-pull driver note: buffer type = 0, polarity = 0 implies open drain buffer type = 0, polarity = 1 implies open source note: if gpio pme enable is 0, this bit is ignored. 2 gpio pme wol select three types of wakeup events are supported: magic pa cket, phy link up, and wakeup pin(s) assertion. wakeup pin(s) are selected via the gpio wake 0-10 (gpiowkn) field of the general purpose io wake enable and polarity register (gpio_wake) . the wakeup enables are specified in bytes 1eh and 1fh of the eeprom. this bit selects whet her magic packet or link up wakeup events are supported. 0 = magic packet wakeup supported. 1 = phy link up wakeup supported (not supported in external phy mode). note: if gpio pme enable is 0, this bit is ignored. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 89 lan9730/lan9730i 4.7.2 eeprom defaults the signature value of 0xa5 is stored at address 0. a different signature value indicates to the eeprom controller that no eeprom or an un-programmed eeprom is attached to the de vice. in this case, the hardware default values are used, as shown in table 4-59 . refer to section 4.3.1.6, "usb descriptors" for further information about the default usb values. 4.7.3 eeprom auto-load certain system level resets (usb reset, por, nreset, and srst) cause the eeprom conten ts to be loaded into the device. after a reset, the eepr om controller attempts to read the first byte of data from the eeprom. if the value 0xa5 is read from the first address, then the eeprom controller will assume that an external serial eeprom is present. the eeprom controller will then load the entire contents of the eeprom into an internal 512 byte sram. the contents of the sram are accessed by the ctl (usb control block) as needed (i.e., to fill get descriptor commands). a detailed explanation of the eeprom byte ordering with respect to the mac address is given in section 6.4.3, "mac address low register (addrl)" . if an 0xa5h is not read from the first address, the eeprom controller will end in itialization. the default values, as spec- ified in table 4-59 , will then be assumed by the associated registers. it is then the responsibility of the host lan driver software to set the ieee address by writing to the macs addrh and addrl registers. the device may not respond to the usb host until the eepr om loading sequence has comp leted. therefore, after reset, the usb phy is kept in the disconnec t state until the eeprom load has completed. 1 gpio10 detection select this bit selects the detection mode for gpio10 when operating in pme mode. in pme mode, gpio10 is usable in both internal and external phy mode as a wakeup pin. this parameter defines whether the wakeup should occur on an active high or active low signal. 0 = active-low detection for gpio10 1 = active-high detection for gpio10 note: if gpio pme enable is 0, this bit is ignored. 0 reserved table 4-59: eeprom defaults field default value mac address ffffffffffffh full-speed polling interval (ms) 01h hi-speed polling interval (ms) 04h configuration flags 04h maximum power (ma) fah vendor id 0424h product id 9730h note: the configuration flags are affected by the rmt_wkp strap. note: the usb reset only loads the mac address. table 4-58: gpio pme flags (continued) bits description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 90 ? 2012-2015 microchip technology inc. 4.7.4 eeprom ho st operations after the eeprom controller has finished reading (or attempti ng to read) the eeprom afte r a system-level reset, the host is free to perform other eeprom operations. eepro m operations are performed using the eeprom command (e2p_cmd) and eeprom data (e2p_data) registers. section 6.3.12, "eeprom command register (e2p_cmd)" provides an explanation of t he supported eeprom operations. if the eeprom operation is the write lo cation (write) or write all (wral) commands, the host must first write the desired data into the e2p_data register. the host must then issue the write or wral command using the e2p_cmd register by setting the epc_cmd field appropriately. if the operation is a write, the epc_addr field in e2p_cmd must also be set to the desired location. the command is executed when the host sets the epc_bsy bit high. the com- pletion of the operation is indica ted when the epc_bsy bit is cleared. if the eeprom operation is the read location (read) operat ion, the host must issue the read command using the e2p_cmd register with the epc_addr set to the desired lo cation. the command is exec uted when the host sets the epc_bsy bit high. the completion of the operation is indica ted when the epc_bsy bit is cleared, at which time the data from the eeprom may be read from the e2p_data register. other eeprom operations are performed by writing the appropriat e command to the e2p_cm d register. the command is executed when the host sets the epc _bsy bit high. the completi on of the operation is indicated when the epc_bsy bit is cleared. in all cases, the ho st must wait for epc_bsy to clear be fore modifying the e2p_cmd register. if an operation is attemp ted, and an eeprom device does not respond wit hin 30 ms, the device will time-out, and the epc time-out bit (epc_to) in the e2p_cmd register will be set. figure 4-20 illustrates the host accesses required to perform an eeprom read or write operation. note: the eeprom device powers-up in the erase/write disabled state. to m odify the contents of the eeprom, the host must first issue the ewen command. figure 4-20: eeprom access flow diagram idle write data register write command register read command register idle write command register read command register read data register busy bit = 0 busy bit = 0 eeprom write eeprom read downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 91 lan9730/lan9730i 4.7.4.1 supported eeprom operations the eeprom controller supports the following eeprom opera tions under host control via the e2p_cmd register. the operations are commonly supported by 93c46 eeprom devi ces. a description and functional timing diagram is pro- vided below for each operation. refer to the e2p_cmd register description in section 6.3.12, "eeprom command register (e2p_cmd)" for e2p_cmd field settings for each command. erase (erase location): if erase/write operations are enabled in t he eeprom, this command will erase the location selected by the epc address field (epc_addr). the epc_t o bit is set if the eeprom does not respond within 30 ms. eral (erase all): if erase/write operations are enabled in the eepr om, this command will initiate a bulk erase of the entire eeprom. the epc_to bit is set if t he eeprom does not respond within 30 ms. figure 4-21: eeprom erase cycle figure 4-22: eeprom eral cycle erase cycle 1 eeclk eedio (input) eedio (output) eecs 11 a6 a0 t csl eral cycle 0 eeclk eedio (input) eedio (output) eecs 10 10 t csl downloaded from: http:///
lan9730/lan9730i ds00001946a-page 92 ? 2012-2015 microchip technology inc. ewds (erase/write disable): after issued, the eeprom will ignore erase and write commands. to re-enable erase/ write operations issue the ewen command. ewen (erase/write enable): enables the eeprom for erase and write operations. the eeprom will allow erase and write operations until the erase/write disabl e command is sent, or until power is cycled. figure 4-23: eeprom ewds cycle note: the eeprom device will power-up in the erase/write-di sabled state. any erase or write operations will fail until an erase/write enable command is issued. figure 4-24: eeprom ewen cycle ewds cycle 0 eeclk eedio (input) eedio (output) eecs 10 00 t csl ewen cycle 0 eeclk eedio (input) eedio (output) eecs 10 11 t csl downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 93 lan9730/lan9730i read (read location): this command will cause a read of the eepr om location pointed to by epc address (epc_addr). the result of the read is available in the e2p_data register. write (write location): if erase/write operat ions are enabled in the eeprom, this command will cause the contents of the e2p_data register to be written to the eeprom location selected by the epc address field (epc_addr). the epc_to bit is set if the eeprom does not respond within 30 ms. figure 4-25: eeprom read cycle figure 4-26: eepr om write cycle read cycle 1 10 a6 eecs eeclk eedio (output) a0 d7 d0 eedio (input) t csl write cycle 0 eeclk eedio (input) eedio (output) eecs 11 a6 a0 d7 d0 t csl downloaded from: http:///
lan9730/lan9730i ds00001946a-page 94 ? 2012-2015 microchip technology inc. wral (write all): if erase/write operatio ns are enabled in the eeprom, this co mmand will cause the contents of the e2p_data register to be written to every eeprom memory location. the epc_to bit is set if the eeprom does not respond within 30 ms. table 4-60, "required eeclk cycles" , shown below, shows the number of eeclk cycles required for each eeprom operation. 4.7.4.2 host initiated eeprom reload the host can initiate a reload of the eeprom by i ssuing the reload command via the e2p command (e2p_cmd) register. if the first byte read from the eeprom is not 0xa5 , it is assumed that the eeprom is not present or not pro- grammed, and the reload will fail. the data loaded bit of th e e2p_cmd register indicates a successful reload of the eeprom. 4.7.4.3 eeprom command and data registers refer to section 6.3.12, "eeprom co mmand register (e2p_cmd)" and section 6.3.13, "eepr om data register (e2p_data)" for a detailed description of these registers. su pported eeprom oper ations are described in these sec- tions. 4.7.4.4 eeprom timing refer to section 7.5.5, "eeprom timing" for detailed eeprom timing specifications. figure 4-27: eeprom wral cycle table 4-60: required eeclk cycles operation required eeclk cycles erase 10 eral 10 ewds 10 ewen 10 read 18 write 18 wral 18 note: it is not recommended to use the reload command as part of normal operation, as race conditions can occur with usb commands that access descriptor data. it is best for the host to issue an srst to reload the eeprom data. wral cycle 0 eeclk eedio (input) eedio (output) eecs 1 d7 d0 0 01 t csl downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 95 lan9730/lan9730i 4.7.5 example of eeprom format interpretation table 4-61 and table 4-62 provide an example of how the co ntents of an eeprom are formatted. table 4-61 is a dump of the eeprom memory (256-byte eeprom), while table 4-62 illustrates, byte by byte, how the eeprom is formatted. table 4-61: dump of eeprom memory offset byte value 0000h a5 12 34 56 78 9a bc 01 0008h 04 04 09 04 0a 11 12 16 0010h 10 1f 00 00 00 00 12 27 0018h 12 30 12 39 12 42 00 04 0020h 8a 00 0a 03 53 00 4d 00 0028h 53 00 43 00 12 03 4c 00 0030h 41 00 4e 00 39 00 37 00 0038h 33 00 30 00 10 03 30 00 0040h 30 00 30 00 35 00 31 00 0048h 32 00 33 00 12 01 00 02 0050h ff 00 ff 40 24 04 30 97 0058h 00 01 01 02 03 01 09 02 0060h 27 00 01 01 00 a0 fa 09 0068h 04 00 00 03 ff 00 ff 00 0070h 12 01 00 02 ff 00 ff 40 0078h 24 04 30 97 00 01 01 02 0080h 03 01 09 02 27 00 01 01 0088h 00 a0 fa 09 04 00 00 03 0090h - 00ffh ff 00 ff 00 .................... table 4-62: eeprom example - 256 byte eeprom eeprom address eeprom contents (hex) description 00h a5 eeprom programmed indicator 01h - 06h 12 34 56 78 9a bc mac address 12 34 56 78 9a bc 07h 01 full-speed polling interval for interrupt endpoint (1 ms) 08h 04 hi-speed polling interval for interrupt endpoint (4 ms) 09h 04 configuration flags - the device is bus powered and supports remote wakeup, nspd_led = speed indicator, nlnka_led = link and activity indicator, nfdx_led = full duplex link indicator. 0ah - 0bh 09 04 language id descriptor 0409h, english 0ch 0a manufacturer id string descriptor length (10 bytes) 0dh 11 manufacturer id string desc riptor eeprom word offset (11h); corresponds to eeprom byte offset 22h 0eh 10 product name string descriptor length (16 bytes) 0fh 16 product name string descriptor eeprom word offset (16h); corresponds to eeprom byte offset 2ch 10h 10 serial number string descriptor length (16 bytes) 11h 1e serial number string descr iptor eeprom word offset (1eh); corresponds to eeprom byte offset 3ch 12h 00 configuration string desc riptor length (0 bytes - na) downloaded from: http:///
lan9730/lan9730i ds00001946a-page 96 ? 2012-2015 microchip technology inc. 13h 00 configuration string descriptor word offset (dont care) 14h 00 interface string descriptor length (0 bytes - na) 15h 00 interface string descriptor word offset (dont care) 16h 12 hi-speed device descriptor length (18 bytes) 17h 26 hi-speed device descriptor word offset (26h); corresponds to eeprom byte offset 4ch 18h 12 hi-speed configuration and interface descriptor length (18 bytes) 19h 2f hi-speed configuration and interface descriptor word offset (2fh); corresponds to eeprom byte offset 5eh 1ah 12 full-speed device descriptor length (18 bytes) 1bh 38 full-speed device descriptor word offset (38h); corresponds to eeprom byte offset 70h 1ch 12 full-speed configuration and in terface descriptor length (18 bytes) 1dh 41 full-speed configuration and inte rface descriptor word offset (41h); corresponds to eeprom byte offset 82h 1eh 00 gpio7:0 wake enables - gpio7:0 not used for wakeup signaling 1fh 04 gpio10:8 wake enables - gpio10 used for wakeup signaling 20h 8a gpio pme flags - pme signaling enabled via low level, push-pull driver, gpio10 active high detection. 21h 00 pad byte - used to align following descriptor on word boundary 22h 0a size of manufacturer id string descriptor (10 bytes) 23h 03 descriptor type (string descriptor - 03h) 24h - 2bh 53 00 4d 00 53 00 43 00 manufacturer id string (smsc in unicode) 2ch 10 size of product name string descriptor (16 bytes) 2dh 03 descriptor type (string descriptor - 03h) 2eh - 3bh 4c 00 41 00 4e 00 39 00 37 00 33 00 30 00 product name string (lan9730 in unicode) 3ch 10 size of serial number string descriptor (16 bytes) 3dh 03 descriptor type (string descriptor - 03h) 3eh - 4bh 30 00 30 00 30 00 35 00 31 00 32 00 33 00 serial number string (0005123 in unicode) 4ch 12 size of hi-speed device descriptor in bytes (18 bytes) 4dh 01 descriptor type (device descriptor - 01h) 4eh - 4fh 00 02 usb specification number that the device complies with (0200h) 50h ff class code 51h 00 subclass code 52h ff protocol code 53h 40 maximum packet size for endpoint 0 54h - 55h 24 04 vendor id (0424h) 56h - 57h 30 97 product id (9730h) 58h - 59h 00 01 device release number (0100h) 5ah 01 index of manufacturer string descriptor 5bh 02 index of product string descriptor 5ch 03 index of serial number string descriptor 5dh 01 number of possible configurations table 4-62: eeprom example - 256 byte eeprom (continued) eeprom address eeprom contents (hex) description downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 97 lan9730/lan9730i 5eh 09 size of hi-speed configuration descriptor in bytes (9 bytes) 5fh 02 descriptor type (configuration descriptor - 02h) 60h - 61h 27 00 total length in bytes of data returned (0027h = 39 bytes) 62h 01 number of interfaces 63h 01 value to use as an argument to select this configuration 64h 00 index of string descriptor describing this configuration 65h a0 bus powered and remote wakeup enabled 66h fa maximum power consumption is 500 ma 67h 09 size of hi-speed interface descriptor in bytes (9 bytes) 68h 04 descriptor type (interface descriptor - 04h) 69h 00 number identifying this interface 6ah 00 value used to select alternative setting 6bh 03 number of endpoints used for this interface (less endpoint 0) 6ch ff class code 6dh 00 subclass code 6eh ff protocol code 6fh 00 index of string descriptor describing this interface 70h 12 size of full-speed device descriptor in bytes (18 bytes) 71h 01 descriptor type (device descriptor - 01h) 72h - 73h 00 02 usb specification number that the device complies with (0200h) 74h ff class code 75h 00 subclass code 76h ff protocol code 77h 40 maximum packet size for endpoint 0 78h - 79h 24 04 vendor id (0424h) 7ah - 7bh 30 97 product id (9730h) 7ch - 7dh 00 01 device release number (0100h) 7eh 01 index of manufacturer string descriptor 7fh 02 index of product string descriptor 80h 03 index of serial number string descriptor 81h 01 number of possible configurations 82h 09 size of full-speed configuration descriptor in bytes (9 bytes) 83h 02 descriptor type (configuration descriptor - 02h) 84h - 85h 27 00 total length in bytes of data returned (0027h = 39 bytes) 86h 01 number of interfaces 87h 01 value to use as an argument to select this configuration 88h 00 index of string descriptor describing this configuration 89h a0 bus powered and remote wakeup enabled 8ah fa maximum power consumption is 500 ma 8bh 09 size of full-speed interface descriptor in bytes (9 bytes) 8ch 04 descriptor type (interface descriptor - 04h) 8dh 00 number identifying this interface 8eh 00 value used to select alternative setting table 4-62: eeprom example - 256 byte eeprom (continued) eeprom address eeprom contents (hex) description downloaded from: http:///
lan9730/lan9730i ds00001946a-page 98 ? 2012-2015 microchip technology inc. 4.8 customized operation without eeprom the device provides the capability to customize operation without the use of an eeprom. descriptor information and initialization quantities normally fetched from eeprom and used to initialize descriptors and elements of the system control and status registers may be specified via an alternate mechanism. this alternate mechanism involves the use of the descriptor ram in conjunction with the attributes registers and select elements of the system control and status registers . the software device driver orchestrates the process by performing the following actions in the order indi- cated: initialization of scsr elements in lieu of eeprom load attribute register initialization descriptor ram initialization enable descriptor ram and flag attribute registers as source inhibit reset of select scsr elements the following subsections explain these action s. the attributes registers must be wr itten prior to initializing the descrip- tor ram. failure to do this will prevent the rmt_wkup flag from being overwritten by the bmattributes of the config- uration descriptor. 4.8.1 initializat ion of scsr elements in lieu of eeprom load during eeprom operation, the follo wing register fields are initialized by the hardware using the val ues contained in the eeprom. in the absence of an eeprom, the software device driver mu st initialize these quantities: mac address high register (addrh) and mac address low register (addrl) led select (led_sel) bit of the led general purpose io configur ation register (led_gpio_cfg) gpio wake 0-10 (gpiowkn) field of the general purpose io wake enable and polarity register (gpio_wake) 4.8.2 attribute register initialization the attributes registers are as follows: hs descriptor attributes register (hs_attr) fs descriptor attributes register (fs_attr) string descriptor attributes register 0 (strng_attr0) string descriptor attributes register 1 (strng_attr1) flag attributes register (flag_attr) all of these registers, with the exceptio n of flag_attr, contain fields defining the lengths of the descriptors written into the descriptor ram. if the descriptor is not written in to the descriptor ram, the associated entry in the attributes register must be written as 0. writing an erroneous or illegal length will result in untoward operation and unexpected results. the flag attributes register (flag_attr) provides the mechanism to initialize components of the configuration flags and gpio pme flags that are stand-alone and not part of any other system control and status register. during eeprom operation, the analogous fields in this register are read by the hardware from the eeprom and are not avail- able to the software for read-back or modification. 8fh 03 number of endpoints used for this interface (less endpoint 0) 90h ff class code 91h 00 subclass code 92h ff protocol code 93h 00 index of string descriptor describing this interface 94h - ffh - data storage for use by host as desired note: the software device driver must initialize thes e registers prior to initializing the descriptor ram. table 4-62: eeprom example - 256 byte eeprom (continued) eeprom address eeprom contents (hex) description downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 99 lan9730/lan9730i 4.8.3 descriptor ram initialization the descriptor ram contents are initialized using the data port registers. the data port regi sters are used to select the descriptor ram and write the descriptor elements into it. the descriptor ram is 512 bytes in length. every descriptor written into the descriptor ram must be dword al igned. the attributes registers discussed in section 4.8.2 must be written with the length of the descriptors written into the descriptor ram. if a descriptor is not used, hence not written into descriptor ram, its length must be writte n as 0 into the associated attribute register. the descriptors must be written in the following order, star ting at address 0 of the ram and observing the dword align- ment rule: language id descriptor manufacturing string descriptor (string index 1) product name string descriptor (string index 2) serial number string descriptor (string index 3) configuration string descriptor (string index 4) interface string descriptor (string index 5) hs device descriptor hs configuration descriptor fs device descriptor fs configuration descriptor an example of descriptor ram use is illustrated in figure 4-28 . as in the case of descriptors specified in eeprom, the following restrictions appl y to descriptors written into descriptor ram: 1. for device descriptors, the only valid values for the length are 0 and 18. the descriptor size for the device descriptors specified in the descriptor ram is a don't ca re and always overwritten by hw to 0x12 when trans- mitting the descriptor to the host. 2. the descriptor type for device descriptors specified in th e descriptor ram is a don't care and is always overwrit- ten by hw to 0x1 when transmitting the descriptor to the host. 3. for the configuration and interface descriptor, the only valid values for the length are 0 and 18. the descriptor size for the device descriptors specif ied in the descriptor ram is a don't care and always overwritten by hw to 0x12 when transmitting the descriptor to the host. 4. the descriptor type for the configuration descriptors sp ecified in the descriptor ram is a don't care and always overwritten by hw to 0x2 when tr ansmitting the descriptor to the host. 5. if a string descriptor does not exist in the descriptor ram, the referencing descriptor must contain 00h for the respective string index field. 6. if all string descriptor lengths are ze ro than a language id will not be supported. note: the bmattributes field of the hs and fs descriptors in descriptor ram (if present) must be consistent with the contents of the flag attributes register (flag_attr) . note: the attributes registers must be in itialized before the descriptor ram. note: address 0 of the descriptor ram is always reserved fo r the language id descriptor, even if it will not be supported. note: the first entry in the descriptor ram is always rese rved for the language id descriptor, even if it will not be supported. note: descriptors specified having bcdusb, bmaxpacketsize0, and bnumconfigurations fields defined with val- ues other than 0200h, 40h, and 1, respectively, will result in unwanted behavior and untoward results. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 100 ? 2012-2015 microchip technology inc. the ram test mode enable (testen) bit must be deasserted after programming the descriptor ram. figure 4-28: descriptor ram example language id descriptor manufacturing string descriptor product name string descriptor serial number string descriptor configuration string descriptor interface string descriptor hs device descriptor hs configuration and interface descriptor fs device descriptor fs configuration and interface descriptor 0 1 2 3 4 5 6 7 8 9 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e dataport addr = unused space required for alignment purposes downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 101 lan9730/lan9730i 4.8.4 enable descriptor ram and fl ag attribute registers as source the eeprom emulation enable (eem) bit of the hardware configuration register (hw_cfg) must be configured by the software device driver to use the descriptor ram and the attributes registers for custom operation. upon assertion of eeprom emulation enable (eem) , the hardware will utilize the descriptor information contained in the descriptor ram, the attributes registers, and the values of the items listed in section 4.8.1 to facilitate custom operation. 4.8.5 inhibit reset of select scsr elements the software device driver must take care to ensure that the contents of the descriptor ram and scsr register content critical to custom operation using descriptor ram are pres erved across reset operations other than por. the driver must configure the reset protection (rst_protect) bit of the hardware configuration register (hw_cfg) in order to accomplish this. the following registers have contents that can be preserved across all resets other than por. consult the registers description for additional details. descriptor ram attributes registers mac address high register (addrh) and mac address low register (addrl) hardware configuration register (hw_cfg) led general purpose io configur ation register (led_gpio_cfg) general purpose io wake enable and polarity register (gpio_wake) 4.9 device clocking the device requires a fixed-frequency 25 mhz clock source. this is typically provided by attaching a 25 mhz crystal to the xi and xo pins. the clock can optionally be provided by driving the xi input pin with a single-ended 25 mhz clock source. if a single-ended source is selected, the clock inpu t must run continuously for normal device operation. internally, the device generates its required clocks with a p hase-locked loop (pll). it reduces its power consumption in several of its operating states by disa bling its internal pll and derivative clo cks. the 25 mhz clock remains operational in all states where power is applied. 4.10 device power sources the device may be soft powered by the usb bus or self po wered via external power supplies. the following external 3.3 v power supplies are required when power is not being furnished by the usb bus: vdd33io, vdd33a the device includes an internal 1.2 v regulator which provi des power to the internal core logic. this regulator may be optionally disabled if an external 1.2 v power source is av ailable. the internal core regulator is controlled via the core_reg_en pin. when disabled, +1.2 v must be supplied to the device by an external source. refer to chapter 3.0 for information on proper power connections when enabling or disabling the internal core regulator. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 102 ? 2012-2015 microchip technology inc. 4.11 power states the following power states are featured. normal (unconfigured and configured) suspend (suspend0, suspe nd1, suspend2, and suspend3) figure 4-29 illustrates the power states and allowed state transitions. 4.11.1 normal state the normal state is the fully functiona l state of the device. the are two flav ors of the normal state, normal con- figured and normal unconfigured. in the configured vari ation, all chip subsystem modules are enabled. the uncon- figured variation has only a subset of the modules enabled. the reduced functionality allows for power savings. this normal state is entered by any of the following methods: a system reset is asserted. the device is suspended and the host issues resume signaling. the device is suspended and a wake event is detected. 4.11.1.1 unconfigured upon initially entering the normal state, the device is un configured. the device transiti ons to the normal configured state upon the host completion of the usb configuration. it is possible for the device to be deconfigured by the host after being placed in the normal configured state, via a set_configuration command. in this case , the cpm must place the device back into the normal unconfigured state. 4.11.1.2 reset operation after a system reset, the device is placed into the normal unconfigured state. when in the no rmal state, the ready bit in the power management contro l register (pmt_ctl) is set. this ready bit is useful to the host after a usb reset occurs. in this case, it indicates that the values in the eeprom have been completely loaded. figure 4-29: power states note: it is not possible to transition from suspend2 to normal configured if suspend2 was entered via a transition from normal unconfigured. normal (configured) suspend0 suspend1 suspend2 usb resume || phy linkup || wol || gpio usb suspend usb resume || gpio usb suspend usb resume || energy detect || gpio usb suspend por || nreset || usb reset || srst normal (unconfigured) configured deconfigured usb resume || gpio usb suspend suspend3 usb suspend usb resume || phy linkup || frame recd || gpio downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 103 lan9730/lan9730i 4.11.1.3 suspend operation when returning to the normal state from the suspend state, the usb context is maintained. after entering the nor- mal state, the ready bit in the pmt_ctl register is asserted. 4.11.2 suspend states the suspend state is entered after the usb host suspends the device. four variations of the usb suspend state are available. each state offers different options in terms of power consumption and wakeup support. a suspend state is entered via a tr ansition from the normal state. the suspend_mode field in the power man- agement control register (pmt_ctl) indicates which suspend state is to be used. the host sets the value of this field to select the desired suspend stat e, then sends suspend signaling. a tran sfer back to the normal state occurs when the host sends resume signaling or a wakeup event is detected. the device can be suspended from the normal unconfigured state. in this scenario, it is only possible to transition to the suspend2 state. subsequent resume signaling or a wakeup event will cause the device to transition back to the normal unconfigured state. 4.11.2.1 reset from suspend all suspend states must respond to a usb reset and pin reset, nreset. the application of these resets result in the devices hardware being re-initialized and placed into the normal unconfigured state. 4.11.2.2 suspend0 this state is entered from the norm al state when the device is suspended and the suspend_mode field in the power management control register (pmt_ctl) is set to 00b. refer to section 4.12.2.1, "enabling gpio wake events" , section 4.12.2.2, "enabling wol wake events" and section 4.12.2.4, "enabling external phy link up wake events" for detailed instructions on how to program events that cause resumption from the suspend0 state. in this state, the mac can optionally be programmed to detect a wake on lan event or magic packet event. gpio events can be programmed to cause wakeup in this state. if gpio7 signals the event, the phy link up enable (phy_linkup_en) bit of the general purpose io wake enable and polarity register (gpio_wake) may be examined to determined whether a phy link up event or pin event occurred. the host may take the device out of the suspend0 state at any time. 4.11.2.3 suspend1 this state is entered from the norm al state when the device is suspended and the suspend_mode field in the power management control register (pmt_ctl) is set to 01b. refer to section 4.12.2.1, "enabl ing gpio wake events" , and section 4.12.2.3, "enabling link status change (energy detect) wake events" for detailed instructions on how to program events that cause resumption from the suspend1 state. in this state, the ethernet phy can be optionally progra mmed for energy detect. gpio events can also be programmed to cause wakeup in this state. the host may take the device out of the suspend1 state at any time. note: if the originating suspend state is suspend2, the host is required to reinitia lize the ethernet phy reg- isters. note: if the device is deconfigured, the suspend_mode field in the power management control register (pmt_ctl) resets to 10b. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 104 ? 2012-2015 microchip technology inc. 4.11.2.4 suspend2 this state is entered from the norm al state when the device is suspend ed and the suspend_mode field in the power management control register (pmt_ctl) is set to 10b. suspend2 is the default suspend mode. refer to section 4.12.2.1, "enabling gpio wake events" for detailed instructions on how to program events that cause resumption from the suspend2 state. this state consumes the least amount of power. in this state, the device may only be awakened by the host or gpio assertion. the state of the ethernet phy is lost when entering suspend2. therefore, host must reinitialize the phy after the device returns to the normal state. 4.11.2.5 suspend3 this state is entered from the norm al state when the device is suspend ed and the suspend_mode field in the power management control register (pmt_ctl) is set to 11b. refer to section 4.12.2.1, "enabling gpio wake events" , section 4.12.2.4, "enabling external phy link up wake events" and section 4.12.2.5, "enabling good frame wake events" for detailed instructions on how to program events that cause resumption from the suspend3 state. in this suspend state, all clocks in the device are enabled and power consumption is similar to the normal state. however, it allows for power savings in the host cpu, whic h greatly exceeds that of the device. the driver may place the device in this state after prolonged perio ds of not receiving any ethernet traffic. this state supports wakeup from gpio a ssertion, phy link up, and on receptio n of a frame passing the filtering con- straints set by the mac control register (mac_cr) . due to the limited amount of rx fifo buffering, it is possible that there will be frames lost when in this state, as the usb resume time greatly exceeds the buffering capacity of the fifo. the wake on lan bit of the wakeup status (wups) field of the power management control register (pmt_ctl) is used to signal wakeup due to reception of a frame passing the aforementioned filtering cons traints. this bit, along with the gpio [10:0] (gpiox_int) bits of the interrupt status register (int_sts) , may be examined to determine the event(s) causing the wakeup. if gpio7 is found to have caused the wakeup, the phy link up enable (phy_link- up_en) bit of the general purpose io wake enable an d polarity register (gpio_wake) may be examined to deter- mined whether a phy link up event or pin event occurred. note: wake on lan events must not be enabled in the wakeup control and status register (wucsr) while operating in the suspend3 state. if any wake on la n event is enabled in wucsr, all received frames will be dropped. the setting of the wake on lan enable (wol_en) bit of the power management control register (pmt_ctl) is a dont care. note: the wake on lan bit of the wakeup status (wups) is used to signal both wake on lan events and wakeup from suspend3 state due to reception of frames passing the filtering constraints set by the mac control register (mac_cr) . in order to interpret the wakeup status (wups) without ambiguity, the soft- ware driver may examine the suspend mode (suspend_mode) field of the power management control register (pmt_ctl) to determine the suspend state it is coming out of. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 105 lan9730/lan9730i 4.12 wake events the following events can wake up/enable the device, depending on the power state. usb host resume wake on lan (wakeup frame, magic packet, perfec t destination address frame, and broadcast frame) reception of a good frame - a frame received wh en no wake on lan events are enabled in the wakeup control and status register (wucsr) that meets the filtering re quirements configured in the mac control register (mac_cr) . phy energy detect phy link up gpio[10:0] table 4-63 illustrates the wake events permit ted in each of the power states. the occurrence of a gpio wake event causes the corresponding bit in the interrupt status register (int_sts) to be set. before suspending the device, the host must ensure that any pending wake events are cleared. otherwise, the device will immediately be awakened after being suspended. table 4-63: power state/wake event mapping power state usb host resume signaling wol good frame phy energy detect phy link up gpio[10:0] suspend0 yes yes no no yes yes suspend1 yes no no yes no yes suspend2 yes no no no no yes suspend3 yes no yes no yes yes downloaded from: http:///
lan9730/lan9730i ds00001946a-page 106 ? 2012-2015 microchip technology inc. 4.12.1 detecting wakeup events the following sections illustrate and discuss the wakeup detection logic. 4.12.1.1 wake detection logic a simplified diagram of the wake ev ent detection logic is shown in figure 4-30 . the functionality of gpios 0-6 and gpios 8-10 is slightly different. the functionality of gpio7 is similar to that of gpios 0-6, with the additional requirement t hat it must cause a wakeup event when enabled for use in phy link up detection. gpios 8-10 are available for use in both internal and exter nal ethernet phy mode of oper ation. their functionality is depicted in figure 4-33 . figure 4-30: wake event de tection block diagram note: diagram does not represent act ual hardware implementation. note: gpios 0-7 are only available for use during internal ethernet phy mode of oper ation. the functionality of gpios 0-6 is depicted in figure 4-31 , while that of gpio7 is shown in figure 4-32 . wol_en (pmt_ctl register) rw wups[1] (pmt_ctl register) suspend0 ed_en (pmt_ctl register) rw wups[0] (pmt_ctl register) mpen (wuscr register) rw mpr (wuscr register) gpio0_det .. . remote_wake pfda_en (wuscr register) rw bcast_en (wuscr register) rw good frame received suspend1 suspend2 suspend3 guen (wuscr register) rw gpio10_det mp detect bcast_fr (wucsr register) bcast detect pfda_fr (wuscr register) pfda detect wufr (wuscr register) wu detect gu detect wuen (wuscr register) rw downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 107 lan9730/lan9730i figure 4-31: detailed gpios 0-6 wake detection logic note: the ime bit is in the hardware configuration register (hw_cfg) . general purpose io configuration reg- ister (gpio_cfg) and general purpose io wake enable a nd polarity register (gpio_wake) must be set accordingly. diagram does not represent actual hardware implementation. figure 4-32: detailed gpio7 wake detection logic gpion_int clear gpion gpiopoln latch gpiodirn gpiodn gpioenn gpiowkn gpion_det ime gpio7_int clear gpio7 gpiopol7 latch gpiodir7 gpiod7 gpioen7 gpiowk7 ime 01 01 gpio7_det suspend0 suspend3 phy_link_en phy_link_up downloaded from: http:///
lan9730/lan9730i ds00001946a-page 108 ? 2012-2015 microchip technology inc. 4.12.1.2 remote wake generation 4.12.1.2.1 wake on lan event or energy detect control bits are implemented in the macs wakeup control and status register (wucsr) to control global unicast frame wakeup, magic packet wakeup, wake up frame de tection wakeup, perfect da frame wakeup, and broadcast frame wakeup: guen, mpen, wuen, pfda_en, and bcast _en, respectively. a composite signal, depending on the state of these control bits and the associated event, is generated and propagated for further processing, as dis- cussed in the following text. two control bits are implemented in the pmt_ctrl scsr : wake on lan enable (wol_en) and energy detect enable (ed_en). depending on the state of these control bi ts, the logic will generate an internal wake event interrupt when the mac detects a wakeup event (global unicast fr ame, wakeup frame, magic packet, perfect destination address frame, or broadcast frame - dep ending on the state of the aforementi oned composite signal), or a phy inter- rupt is asserted (energy detect). two wakeup status (wups) bits are implemented in the scsr space. these bits are set depending on the corresponding wake event. (see section 6.3.8, "power management control register (pmt_ctl)" for further information). if a wake on lan event is detected, then further resolution on the source of the event can be obtained by examining the remote wakeup frame received (wufr) , magic packet received (mpr) , perfect da frame received (pfda_fr) , and broadcast frame received (bcast_fr) status bits in the macs wakeup control and status register (wucsr) . note: the ime bit is in the hardware configuration register (hw_cfg) . general purpose io configuration reg- ister (gpio_cfg) and general purpose io wake enable a nd polarity register (gpio_wake) must be set accordingly. phy link up enable (phy_linkup_en) bit of the general purpose io wake enable and polarity regist er (gpio_wake) must be set if phy link up is used to cause a wake event. diagram does not represent actual hardware implementation. figure 4-33: detailed gpios 8-10 wake detection logic note: the ime bit is in the hardware configuration register (hw_cfg) . led general purpose io configuration register (led_gpio_cfg) and general purpose io wake enable and polarity register (gpio_wake) must be set accordingly. diagram does no t represent actual hardware implementation. note: wake on lan events resulting in the generation of a remote-wake event may only occur when in sus- pend0 state. note: energy detect events resulting in the generation of a remote-wake event may only occur when in sus- pend1 state. gpion_int clear gpion gpiopoln latch gpdirn gpdn gpctln[0] gpiowkn gpion_det ime gpctln[1] downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 109 lan9730/lan9730i wakeup frame detection must be enabled in the mac before detection can occur. likewise, the energy detect interrupt must be enabled in the phy before this interrupt can be used as a wake event. if the devi ce is properly configured, the internal wake event interrupt will cause the assertion of the remote_wake signal on detection of a wake event. 4.12.1.2.2 good frame detection to wakeup on reception of a frame passing t he filtering constraints set solely by the mac control register (mac_cr) , the enables for all wake on lan events contained in the wakeup control and stat us register (wucsr) must be cleared and the desired constraints must be selected in mac_cr. the setting of the wake on lan enable (wol_en) bit of the power management control register (pmt_ctl) is a dont care. the logic will generate an internal wake event interrupt when the mac detects a frame passing the fi ltering constraints (good frame). the wake on lan bit of the wakeup status (wups) field of the power management control register (pmt_ctl) is used to signal wakeup due to reception of the good frame. 4.12.1.2.3 gpio pin gpio pins 0 through 10 may cause the generation of a remote _wake event when properly configured and in any of the suspend states. gpio pins 0 through 7 each have a control bit (gpioen x , 0<= x <=7) in the general purpose io con- figuration register (gpio_cfg) that is used to enable the gpio pin to generate a remote_wake event. gpio pins 8 through 10 have no specific enable bit. the corresponding enable signal for these pins (gpioen y , 8<= y <=10) is derived from the manner in which the pin is progra mmed. ten gpio wakeup status bits (gpiowk y , 8<= y <=10) are available to determine the source of the event. 4.12.1.2.4 phy link up gpio7 may be programmed to signal a wakeup in the suspend0 or suspend3 state on occurrence of a phy link up. the phy link up enable (phy_linkup_en) bit of the general purpose io wake enable and polarity register (gpio_wake) must be set to use gpio7 for this purpose. when used in this mode, th e signal connected to the devices pin is ignored. 4.12.2 enabling wake events 4.12.2.1 enabling gpio wake events the host system must perform th e following steps to enable th e device to assert a remot e_wake event on detection of a gpio wake event. 1. the gpio pin is programmed to facilitate generation of t he wake event. if the pin is one of gpio0 through gpio7, the pin must be enabled to generate the event (gpioenx must be clear in the general purpose io configuration register (gpio_cfg) ). if the pin is one of gpio8 through gpio 10, the pin must be programmed as an input gpio pin (the gpctl and gpdir fields for the pin in the led general purpose io configuration register (led_gpio_cfg) must be set to 00b and 0, respectively). in addition, the pin must be enabled for wakeup and its desired polarity specified in the gpio wake 0-10 (gpiowkn) and gpio polarity 0-10 (gpiopoln) fields, respectively, of the general purpose io wake enable and polarity register (gpio_wake) . 2. the host places the device in the any one of the suspend states by setting the suspend mode (suspend_- mode) field of the power management control register (pmt_ctl) to indicate the desired suspend state, then sends suspend signaling. on detection of an enabled gpio wake event, the devic e will transition back to the normal state and signal a remote_wake event. the host may then examine the gpio [10:0] (gpiox_int) status bits of the interrupt status reg- ister (int_sts) to determine the source of the wakeup. note: good frame reception resulting in the generation of a remote_wake event may only occur when in the suspend3 state. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 110 ? 2012-2015 microchip technology inc. 4.12.2.2 enabling wol wake events the host system must perform th e following steps to enable th e device to assert a remot e_wake event on detection of a wake on lan event. 1. all transmit and receive operations must be halted: a) all pending ethernet tx and rx operations must be completed. b) the mac must be halted. 2. the mac must be configured to detect the desired wake event. this process is explained in section 4.5.5, "wakeup frame detection" for wakeup frames and in section 4.5.6, "magic packet detection" for magic pack- ets. configuring perfect da and broadcast frame wa keup detection is analogous and requires the perfect da wakeup enable (pfda_en) or broadcast wakeup enable (bcast_en) bit to be set in the wakeup control and status register (wucsr) . 3. bit 1 of the wakeup status (wups[1]) in the power management control register (pmt_ctl) must be cleared since a set bit will cause the immediate assertion of wake event when the wake on lan enable (wol_en) bit is set. the wups[1] bit will not clear if the internal mac wakeup event is asserted. 4. set the wake on lan enable (wol_en) bit in the power management control register (pmt_ctl) . 5. the host places the device in the suspend0 state by setting the suspend mode (suspend_mode) field in the power management control register (pmt_ctl) to 00b, to indicate the desired suspend state, then sends suspend signaling. on detection of an enabled event, the device will transition back to the normal state and signal a remote_wake event. the software will then examine the suspend mode (suspend_mode) field of the power management control reg- ister (pmt_ctl) . upon discovering wakeup occurred from suspend0 state, the status bits of the wucsr register may be examined to determine the part icular event that caused the wakeup. 4.12.2.3 enabling link status change (energy detect) wake events the host system must perform th e following steps to enable th e device to assert a remot e_wake event on detection of an ethernet link status change. 1. all transmit and receive operations must be halted: a) all pending ethernet tx and rx operations must be completed. b) the mac must be halted. 2. the phy must be enabled for the energy detect power-down mode this is done by clearing the edpwrdown bit in the phys mode control/status register . enabling the energy detect power-down mode places the phy in a reduced power state. in this mode of operation the ph y is not capable of receiving or transmitting ethernet data. in this state, the phy will assert its internal interrupt if it detects ethernet activity. refer to section 4.6.8.2, "energy detect power-down (edpd)" for more information. 3. bit 0 of the wakeup status (wups[0]) in the power management control register (pmt_ctl) must be cleared, since a set bit will cause the immediate assertion of wake event when energy-detect enable (ed_en) is set. the wups[0] bit will not clear if the internal phy interrupt is asserted. 4. set the energy-detect enable (ed_en) bit in the power management control register (pmt_ctl) . 5. the host places the device in the suspend1 state by setting the suspend mode (suspend_mode) field in the power management control register (pmt_ctl) to 01b, to indicate the desired suspend state, then sends suspend signaling. on detection of ethernet activity (energy), the device will transition back to the normal state and signal a remote_wake event. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 111 lan9730/lan9730i 4.12.2.4 enabling external phy link up wake events the host system must perform th e following steps to enable th e device to assert a remot e_wake event on detection of phy link up. 1. the system software determines that th e link is down by periodically polling the link status bit of the basic status register . alternatively, the driver c an detect assertion of the phy_int bit via the interrupt control endpoint. the driver may also detect phy interrupt assertion by polling the interrupt status register (int_sts) . it then reads the basic status register and finds the link status bit is deasserted. 2. on finding the link down, the host configures the devic e to wake up on phy link up and signal the event using gpio7 as follows: a) the phy link up enable (phy_linkup_en) bit is set in the general purpose io wake enable and polarity register (gpio_wake) to enable gpio7 use in signaling the phy link up event. the gpiowk7 bit is also set in the register to permit its use in wake event generation. the setting of gpiopol7 is a dont care. b) the following additional parameters for gpio7 must be configured in the general purpose io configuration register (gpio_cfg) : gpioen7 = 0, gpiodir7 = 0, gpiobuf7 = dont care. 3. the gpio7_int bit in the interrupt status register (int_sts) must be cleared, since a set bit will cause the immediate assertion of the wake event. 4. the host places the device in the suspend0 or su spend3 state, as approp riate, by setting the suspend mode (suspend_mode) field in the power management control register (pmt_ctl) to 00b or 11b, to indicate the desired suspend state. the host then sends suspend signaling. on detection of phy link up, the device will transition ba ck to the normal state and signal a remote_wake event. the host, in trying to determine the cause of the wake event, may then examine the gpio [10:0] (gpiox_int) status bits of the interrupt status register (int_sts) . on finding gpio7_int set, the software will then use the suspend mode (sus- pend_mode) field of the power management control register (pmt_ctl) and the value of the phy link up enable (phy_linkup_en) bit to determine a phy link up wake event occurred. 4.12.2.5 enabling good frame wake events the host system must perform th e following steps to enable th e device to assert a remot e_wake event on detection of a good frame. 1. the mac filtering is configured by setting the desired constraints in the mac control register (mac_cr) . all wake on lan events contained in the wakeup control and status register (wucsr) must be disabled. the setting of the wake on lan enable (wol_en) bit of the power management control register (pmt_ctl) is a dont care. 2. bit 1 of the wakeup status (wups[1]) in the power management control register (pmt_ctl) must be cleared since a set bit will cause the immediate assertion of wake event. the wups[1] bit will not clear if the internal mac wakeup event is asserted. 3. the host places the device in the suspend3 state by setting the suspend mode (suspend_mode) field in the power management control register (pmt_ctl) to 11b, to indicate the desired suspend state, then sends suspend signaling. on detection of a good frame, the de vice will transition back to the normal state and signal a remote_wake event. the software will then examine the suspend mode (suspend_mode) field of the power management control reg- ister (pmt_ctl) . upon discovering wakeup occurred from suspend3 state, the host may perform desired processing as a result of receiving the good frame. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 112 ? 2012-2015 microchip technology inc. 4.13 resets the device has the following chip level reset sources: power on reset (por) external chip reset (nreset) lite reset (lrst) soft reset (srst) usb reset phy software reset ntrst 4.13.1 power on reset (por) a power on reset occurs whenever power is initially applied to the device, or if power is removed and reapplied to the device. a timer within the device will assert the internal reset fo r approximately 22 ms. 4.13.2 external chip reset (nreset) a hardware reset will occur when the nreset pin is driven low. the ready bit in the pmt_ctrl register can be read by the host, and will read back a 0 until the hardware reset is complete. upon completion of the hardware reset, the ready bit in pmt_ctrl is set high. after the ready bit is set, the device ca n be configured via its cont rol registers. the nreset pin is pulled-high inter- nally by the device and can be left un connected if unused. if used, nreset mu st be driven low for a minimum period as defined in section 7.5.4, "reset and configuration strap timing" . if nreset is unused, the device must be reset following power-up via a soft reset (srst). 4.13.3 lite reset (lrst) this reset is initiated via the lrst bit in the section 6.3.5, "hardware configuration register (hw_cfg)" . it will reset the entire chip with the exception of t he usb device controller and the usb phy (udc, parts of the ctl, and the hsic interface). the pll is not turned off. note: the eeprom contents are loaded by this reset. note: after the assertion of the por, the internal et hernet phy is put into general power down mode. note: after the assertion of nreset, the internal ethe rnet phy is put into general power-down mode. note: this reset does no t cause the usb contents from the eeprom to be reloaded. note: this reset does not place the device into the unconfigured state. note: after the lrst, the usb pipes corresponding to the bu lk-in, bulk-out, and interrupt endpoints must be reset. this process entails clearing the devices e ndpoint_halt feature and resetting the data toggle on the host side. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 113 lan9730/lan9730i 4.13.4 soft reset (srst) a soft reset is initiated by writing a 1 to bit 0 of the hw_cfg register (srst). th is self-clearing bit will return to 0 af ter approximately 2 s, at which time the soft reset is complete . soft reset does not clear control register bits marked as nasr. writing srst = 1 will cause the device to disconnect from the usb shortly after the first good out data packet during the data phase. a brief delay will allow enough time for the device to send the ack for the data stage, but the device will be disconnected (causing a 3-strikes time-out failure) fo r any next transaction (e.g., the status stage, or a repeated data stage, if there were any bus errors). to the usb host, the aforementioned behaviors are the same as what hap- pens during any surprise removal of a usb device. this b ehavior is completely normal, and a compliant host must be tolerant of it. 4.13.5 usb reset a usb reset causes a reset of the entir e chip with the exception of the usb device controller and the hsic interface (udc, parts of the ctl, and the hsic interface). the pll is not turned of f. it will occur after a por, nreset, or srst (these will all force disconnects of the usb bus). after a usb reset, the ready bit in the pmt_ctrl register can be read by the host and will read back a 0 until the eeprom contents are loaded (provided one is present). upon com- pletion of the eeprom contents load, the ready bit in pmt_ ctrl is set high, and the device can be configured via its control registers. 4.13.6 phy software reset the ethernet phy can be reset via two software-initiated resets. refer to section 4.6.9, "phy resets" for details. 4.13.7 ntrst this active-low reset is used by the tap controller. 4.14 configuration straps configuration straps are multi-func tion pins that are driven as outputs during normal operation. during a power on reset (por) or a external chip reset (nreset) , these outputs are tri-stated. the high or low state of the signal is latched following de-assertion of the reset and is used to determine th e default configuration of a pa rticular feature. configura- tion strap signals are noted in chapter 2, "pin description and configuration" . configuration straps are latched as a result of a power on reset (por) or a external chip reset (nreset) . configu- ration straps include internal resistors in order to prevent th e signal from floating when unc onnected. if a particular con- figuration strap is connected to a load, an external pull-up or pull-down shoul d be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be overridden by the addition of an external resistor. note: the eeprom contents are reloaded by this reset. note: after the assertion of the srst the internal et hernet phy is put into general power-down mode. note: this reset does not cause the usb contents from the eeprom to be reloaded. only the mac address is reloaded. note: after the assertion of the usb reset the internal ethernet phy is put into general power-down mode. note: the system designer must guarantee that configuration straps meet the timing requirements specified in section 7.5.4, "reset and configuration strap timing" and section 7.5.3, "power-on configuration strap valid timing" . if configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values note: configuration straps must never be driven as inputs. if required, configurati on straps can be augmented, or overridden with external resistors. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 114 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 115 lan9730/lan9730i 5.0 pme operation the device provides a mechanism for waking up a host system via pme mode of operation. pme signaling is only avail- able while the device is operating in the self-powered mode. figure 5-1 illustrates a typical application. figure 5-1: typical application lan9730/ lan9730i embedded controller chipset hsic pme pme_mode_sel enable hc pme_clear eeprom host processor downloaded from: http:///
lan9730/lan9730i ds00001946a-page 116 ? 2012-2015 microchip technology inc. the host processor is connected to a chipset containing the usb host controller (hc). the usb host controller inter- faces to the device via the hsic usb signals. an embedded controller (ec) signals the chipset and the host processor to power up via an enable signal. the ec interfaces to t he device via three signals. the pme signal is an input to the ec from the device that indicates the occurrence of a wakeup event. the pme_clear (nreset) signal is used to clear the pme. the pme_mode_sel signal is sampled by the device when pme_clear (nreset) is asserted and is used by the device to determine whether it shoul d remain in pme mode or resume normal operation. gpio pins are used for pme handling. the pins used depend on the value of the phy_sel pin, which determines phy mode of operation. in internal phy mode of operation, gpio 0 is reserved for use as an output to signal the pme. gpio1 is reserved for use as the pme_mode_sel input. gpio8 and gpio9 are reserved for analogous use, respectively, in external phy mode of operation. the application scenario in figure 5-1 assumes that the host processor and the chipset are powered off, the ec is oper- ational, and the device is in pme mode, waiting for a wake event to occur. a wake event will result in the device signaling a pme event to the ec, which will then wake up the host processor and chipset via the enable signal. the ec sets pme_mode_sel to determine whether the device is to beg in normal operation or continue in pme mode, and asserts pme_clear (nreset) to clear the pme. the following wake events are supported: wakeup pin(s) the gpio pins not reserved for pme handling have the capability to wake up the device when operating in pme mode. in order for a gpio to generate a wake event, it must be configured as an input. gpios used as wake events must also be enabled by the gpio_wake register, see section 6.3.20, "general purpose io wake enable and polarity register (gpio_wake)" . on por or nreset, all gpios default to inputs and the def ault value of the gpio wake 0-10 (gpio- wkn) field of the gpio_wake register is set from the contents of the eeprom. during pme mode of operation, the gpios used for signaling (gpios 0 and 1 or gpios 8 and 9) are not affected by the register defaults. gpio10 is available as a wakeup pin in external phy mode, while gpios 2-10 are available in internal phy mode. the gpio10 detection select bit in the gpio pme flags byte of the eeprom sets the detection mode for gpio10 in both external and internal phy mode (if enabled via the gpio_w ake register), while gpios 2- 9 are active low (by default) when operating in internal phy mode. magic packet reception of a magic packet when in pme mode will result in a pme being asserted. phy link up detection of a phy link partner when in pme mode will result in a pme being asserted. in order to facilitate pme mode of operation, the gpio pme enable bit in the gpio pme flags field, must be set and all remaining gpio pme flags field bits must be appropriately configured for pulse or level signaling, buffer type and gpio pme wol selection. the pme event is signaled on gp io0 (external phy mode) or gpio8, depending on the phy mode of operation. the pme_mode_sel pin (gpio1 in internal mode of operatio n, gpio9 in external mode of operation) must be driven to the value that determines whether or not the device re mains in pme mode of operation (1) or resumes normal oper- ation (0) when the pme is recognized and clear ed by the ec via pme_clear (nreset) assertion. note: the devices software driver is unaware of pme mode. no internal mechanism exists for the driver to exam- ine the internal hardware to determine the setting of the gpio pme flags read from the eeprom on por or nreset. pme mode is not visible via the gpio register s or via the int_sts regist er. i.e., if a gpio pin or reception of a magic packet results in a pme, the int_sts register is not updated to indicate the occur- rence of the event. the driver has no mechanism availa ble to clear the pme. the driver can not program any gpio register associated with the pme until the ec asserts nreset to clear pme mode. note: when in pme mode, nreset or por will always ca use the contents of the eeprom to be reloaded. note: gpio10 may be used in pme and external phy mode to connect to an external phys link led, in order to generate a phy link up wake event. downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 117 lan9730/lan9730i figure 5-2 flowcharts pme operation while in internal phy mode. the following conditions hold: eeprom configuration: gpio pme enable = 1 (enabled) gpio pme configuration = 0 (pme signaled via level on gpio pin) gpio pme length = 0 (na) gpio pme polarity = 1 (high level signals event) gpio pme buffer type = 1 (push-pull) gpio pme wol select = 0 (magic packet wakeup) gpio10 detection select = 0 (active-low detection) power method = 1 (self powered) mac address for magic packet pme signaling configuration (as determined by phy mode): gpio0 signals pme gpio1 is pme_mode_sel note: a por occurring when pme_mode_sel = 1 and an eeprom present with the gpio pme enable set results in the device entering pme mode. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 118 ? 2012-2015 microchip technology inc. figure 5-2: pme operation wakeup event detected by device? host & chipset powered off device asserts pme true false ec sets pme_mode_sel = 1 and pulses pme_clear low device has eeprom with gpio pme enable =1, enters pme mode ec detects pme ec to wake system to process wakeup event? ec asserts pme_clear device resets and deasserts pme ec sets pme_mode_sel = 0 and asserts pme_clear ec signals enable to host device resets and deasserts pme device connects to usb bus device is in normal operation yes no downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 119 lan9730/lan9730i 6.0 register descriptions 6.1 register nomenclature table 6-1 describes the register bit attributes used throughout this document. 6.2 register memory map table 6-1: register bit types register bit type notation register bit description r read: a register or bit with this attribute can be read. w write: a register or bit with this attribute can be written. ro read only: read only. writes have no effect. rs read to set: this bit is set on read. wo write only: if a register or bit is write-only, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect. wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents is self-cleared after the being set. writes of zero have no effect. contents can be read. ro/lh read only, latch high: this mode is used by the ethernet phy registers. bits with this attribute will stay high until the bit is read. after a read, the bit will remain high, but will change to low if the condit ion that caused the bit to go high is removed. if the bit has not been read, the bit will remain high regardless of if its cause has been removed. nasr not affected by software reset. the state of nasr bits does not change on asser- tion of a software reset. reserved reserved field: reserved fields must be written with zeros, unless otherwise indi- cated, to ensure future compatibility. the valu e of reserved bits is not guaranteed on a read. table 6-2: register memory map address symbol register name 000h - 0ffh scsr system control and status registers 100h - 1fch mcsr mac control and status registers downloaded from: http:///
lan9730/lan9730i ds00001946a-page 120 ? 2012-2015 microchip technology inc. 6.3 system control and status registers table 6-3: device control and status register map address symbol register name 000h id_rev device id and revision register 004h reserved reserved for future expansion 008h int_sts interrupt status register 00ch rx_cfg receive configuration register 010h tx_cfg transmit configuration register 014h hw_cfg hardware configuration register 018h rx_fifo_inf receive fifo information register 01ch tx_fifo_inf transmit fifo information register 020h pmt_ctl power management control register 024h led_gpio_cfg led general purpose io configuration register 028h gpio_cfg general purpose io configuration register 02ch afc_cfg automatic flow control configuration register 030h e2p_cmd eeprom command register 034h e2p_data eeprom data register 038h burst_cap burst cap register 03ch reserved reserved for future expansion 040h dp_sel data port select register 044h dp_cmd data port command register 048h dp_addr data port address register 04ch dp_data0 data port data 0 register 050h dp_data1 data port data 1 register 054h C 060h reserved reserved for future expansion 064h gpio_wake general purpose io wake enable and polarity register 068h int_ep_ctl interrupt endpoint control register 06ch bulk_in_dly bulk-in delay register 070h dbg_rx_fifo_lvl receive fifo level debug register 074h dbg_rx_fifo_ptr receive fifo pointer debug register 078h dbg_tx_fifo_lvl transmit fifo level debug register 07ch dbg_tx_fifo_ptr transmit fifo pointer debug register 080h C 09fh reserved reserved for future expansion 0a0h hs_attr hs descriptor attributes register 0a4h fs_attr fs descriptor attributes register 0a8h strng_attr0 string descriptor attributes register 0 0ach strng_attr1 string descriptor attributes register 1 0b0h flag_attr flag attributes register 0b4h C 0ffh reserved reserved for future expansion downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 121 lan9730/lan9730i 6.3.1 device id and revision register (id_rev) note 6-1 default value is dependent on device revision. address: 000h size: 32 bits bits description type default 31:16 chip id this read-only field identifies the device model. ro 9730h 15:0 chip revision this is the revision of the device. ro note 6-1 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 122 ? 2012-2015 microchip technology inc. 6.3.2 interrupt status register (int_sts) note 6-2 the default depends on the state of the gpio pin. note 6-3 the clearing of a gpiox_int bit also clears the corresponding gpio wake event. address: 008h size: 32 bits bits description type default 31:19 reserved ro - 18 mac reset time out (macrto_int) this interrupt signifies that the 8 ms reset watchdog timer has timed out. this means that the ethernet phy is not supplying the rx_clk or tx_clk. after the timer times out, the mac reset is deasserted asynchronously. r/wc 0b 17 tx stopped (txstop_int) this interrupt is asserted when the stop transmitter (stop_tx) bit in trans- mit configuration register (tx_cfg) is set and the transmitter is halted. note: the source of this interrupt is a pulse. r/wc 0b 16 rx stopped (rxstop_int) this interrupt is issued when the receiver is halted. note: the source of this interrupt is a pulse. r/wc 0b 15 phy interrupt (phy_int) indicates a phy interrupt event. note: depending on configuration, this may report the interrupt status of the internal or the external phy. note: the source of this interrupt is a le vel. the interrupt persists until it is cleared in the phy. ro - 14 transmitter error (txe) when generated, indicates that the transmitter has encountered an error. refer to section 4.4.2.5, "tx error detection" for a description of the condi- tions that will cause a txe. note: the source of this interrupt is a pulse. r/wc 0b 13 tx data fifo underrun interrupt (tdfu) generated when the tx data fifo underruns. note: the source of this interrupt is a pulse. r/wc 0b 12 tx data fifo overrun interrupt (tdfo) generated when the tx data fifo is full, and another write is attempted. note: this interrupt should never occur and indicates a catastrophic hardware error. note: the source of this interrupt is a pulse. r/wc 0b 11 rx dropped frame interrupt (rxdf_int) this interrupt is issued whenever a receive frame is dropped. note: the source of this interrupt is a pulse. r/wc 0b 10:0 gpio [10:0] (gpiox_int) interrupts are generated from the gpios. these interrupts are configured through the gpio_cfg and led_gpio_cfg registers. note: the sources for these interrupts are a level. r/wc note 6-3 note 6-2 downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 123 lan9730/lan9730i 6.3.3 receive configuration register (rx_cfg) address: 00ch size: 32 bits bits description type default 31:1 reserved ro - 0 receive fifo flush setting this bit will reset the rx fifo pointers. sc 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 124 ? 2012-2015 microchip technology inc. 6.3.4 transmit configuration register (tx_cfg) address: 010h size: 32 bits bits description type default 31:3 reserved ro - 2 transmitter enable (tx_on) when this bit is set, the transmitter is enabled. any data in the tx fifo will be sent. this bit is cleared automatically when stop_tx is set and the transmit- ter is halted. r/w 0b 1 stop transmitter (stop_tx) when this bit is set, the transmitter will finish the current frame being read from the tx fifo, and will then stop transmitting. when the transmitter has stopped, this bit will clear. all writes to this bit are ignored while this bit is high. note: after this bit clears, there will be no tx ethernet frame data in the tx data path. sc 0b 0 transmit fifo flush setting this bit will reset the tx fifo pointers. sc 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 125 lan9730/lan9730i 6.3.5 hardware configuration register (hw_cfg) address: 014h size: 32 bits bits description type default 31:17 reserved ro - 16 eeprom emulation enable (eem) this bit is used to select the source of descriptor information and configuration flags when no eeprom is present. 0 = use defaults as specified in section 4.7.2, "eeprom defaults" . 1 = use descriptor ram and attributes registers. note: this bit affects operation only when an eeprom is not present. this bit has no effect when an eeprom is present. note: this field is protected by reset protection (rst_protect) . r/w 0b 15 reset protection (rst_protect) setting this bit protects select fields of certain registers from being affected by resets other than por. note: this field is protected by reset protection (rst_protect) . r/w 0b 14:13 reserved ro - 12 bulk-in empty response (bir) this bit controls the response to bulk-in tokens when the rx fifo is empty. 0 = respond to the in token with a zlp 1 = respond to the in token with a nak r/w 0b 11 activity led 80 ms bypass (ledb) when set, the activity led on/off time is reduced to approximately 15 s/ 15 s. r/w 0b 10:9 rx data offset (rxdoff) this field controls the amount of offset, in bytes, that is added to the beginning of an rx data packet. the start of the valid data will be shifted by the amount of bytes specified in this field. an offset of 0-3 bytes is a valid number of offset bytes. note: this register may not be modified after the rx data path has been enabled. r/w 00b 8 stall bulk-out pipe disable (sbp) this bit controls the operation of the bulk-out pipe when the fct detects the loss of sync condition. refer to section 4.4.2.5, "tx error detection" for details. 0 = stall the bulk-out pipe when loss of sync detected. 1 = do not stall the bulk-out pipe when loss of sync detected. r/w 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 126 ? 2012-2015 microchip technology inc. 7 internal mii visibility enable (ime) this register enables a subset of the mii interface to be visible on unused pins when configured for the internal ethernet phy mode. the pins controlled by the ime bit are comprised of the pins listed in table 2-1, "mii interface pins" and the nphy_int pin. 0 = the mii signals are not visible. the mii pins function as inputs. 1 = the mii signals are visible. the mii pins function as outputs. note: this register has no affect when using an external phy. note: the ime has priority over the gpio_cfg register. when ime is asserted, the pins crs, mdc, mdio, col, txd3, txd2, txd1, and txd0 can not be configured for gpio operation. rw 0b 6 discard errored received ethernet frame (drp) this bit will cause errored ethernet frames to be discarded when enabled. 0 = do not discard errored ethernet frames. 1 = discard errored ethernet frames. r/w 0b 5 multiple ethernet frames per usb packet (mef) this bit enables the usb transmit direction to pack multiple ethernet frames per usb packet whenever possible. 0 = support no more than one ethernet frame per usb packet. 1 = support packing multiple ethernet frames per usb packet. note: the urx supports this mode by default. r/w 0b 4 eeprom time-out control (etc) this bit controls the length of time used by the eepom controller to detect a time-out. 0 = time-out occurs if no response received from eeprom after 30 ms. 1 = time-out occurs if no response received from eeprom after 1.28 s. r/w 0b 3 soft lite reset (lrst) writing 1 generates the lite software reset of the device. a lite reset will not affect the udc. additionally, the contents of the eeprom will not be reloaded. this reset will not cause the usb phy to be discon- nected. this bit clears after the reset sequence has completed. sc 0b 2 phy select (psel) this bit indicates whether an internal or external ethernet phy is being used. 0 = internal ethernet phy is used. 1 = external ethernet phy is used. ro note 6-4 1 burst cap enable (bce) this register enables use of the burst cap register, section 6.3.14, "burst cap register (burst_cap)" . 0 = burst cap register is not used to limit the tx burst size. 1 = burst cap register is used to limit the tx burst size. r/w 0b bits description type default downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 127 lan9730/lan9730i note 6-4 the phy_sel pin determines the default value. 0 soft reset (srst) writing 1 generates a software initiated reset of the device. if an external ethernet phy is used, it will be reset as well. a software reset will result in the contents of the eeprom being reloaded. while the reset sequence is in progress, the usb phy will be disconnected. after the device has been reinitialized, it will take the phy out of the discon- nect state and be visible to the host. sc 0b bits description type default downloaded from: http:///
lan9730/lan9730i ds00001946a-page 128 ? 2012-2015 microchip technology inc. 6.3.6 receive fifo informatio n register (rx_fifo_inf) address: 018h size: 32 bits bits description type default 31:16 reserved ro - 15:0 rx data fifo used space (rxdused) reads the amount of space in bytes used in the rx data fifo. for each receive frame, this field is increment ed by the length of the receive data rounded up to the nearest dword (if the payload does not end on a dword boundary). ro 0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 129 lan9730/lan9730i 6.3.7 transmit fifo informat ion register (tx_fifo_inf) address: 01ch size: 32 bits bits description type default 31:16 reserved ro - 15:0 tx data fifo free space (tdfree) reads the amount of space, in bytes, available in the tx data fifo. ro 2000h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 130 ? 2012-2015 microchip technology inc. 6.3.8 power management control register (pmt_ctl) this register controls the power management features. address: 020h size: 32 bits bits description type default 31:10 reserved ro - 9 resume clears remote wakeup status (res_clr_wkp_sts) when set, the remote wakeup frame received (wufr) , magic packet received (mpr) , perfect da frame received (pfda_fr) and broadcast frame received (bcast_fr) status signals in the wakeup control and sta- tus register (wucsr) will clear upon the completion of a resume sequence. when set, this bit also affects the wups field. wups[1] will clear upon com- pletion of a resume event. when cleared, the wakeup status signals are not cleared after a resume. r/w 0b 8 resume clears remote wakeup enables (res_clr_wkp_en) when asserted, all wakeup enable bits are cleared after a resume sequence, initiated from a remote wakeup, completes. resumes initiated by the host do not clear the wakeup enables. note: global unicast wakeup enable (guen) , perfect da wakeup enable (pfda_en) , wakeup frame enable (wuen) , magic packet enable (mpen) , and broadcast wakeup enable (bcast_en) are not included. r/w 1b 7 device ready (ready) when set, this bit indicates that the device is in the normal state and the ini- tial hardware configuration of the device has been completed. note: this bit is useful for events (usb reset) that do not trigger a soft disconnect. note: in the case wher e no phy clocks are present to complete a system reset, this bit will not be set unt il the watchdog timer expires. this is applicable for a lite reset and when transitioning to the normal configured state. ro 0b 6:5 suspend mode (suspend_mode) indicates which suspend power state to use after the host suspends the device. if the device is deconfigured, it transitions to the normal unconfigured state and this register will reset to the value 10b. suspend_mode encoding: 00 = suspend0 01 = suspend1 10 = suspend2 11 = suspend3 note: it is not valid to select any suspend variant besides suspend2 when in the normal unconfigured state. r/w 10b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 131 lan9730/lan9730i 4 phy reset (phy_rst) writing a '1' to this bit resets the phy. the internal logic automatically holds the phy reset for a minimum of 2 ms. when the phy is released from reset, this bit is automatically cleared. all writes to this bit are ignored while this bit is high. note: the device will nak all usb transfers until the phy reset completes. sc 0b 3 wake on lan enable (wol_en) enables wol as a wakeup event. this bit is automatically cleared at the completion of a resume sequence if resume clears remote wake up enables (res_clr_wkp_en) is set. r/w 0b 2 energy-detect enable (ed_en) enables energy-detect as a wakeup event. this bit is automatically cleared at the completion of a resume sequence if resume clears remote wake up enables (res_clr_wkp_en) is set. r/w 0b 1:0 wakeup status (wups) this field indicates the cause of the current wakeup event. the wups[0] and wups[1] bits are set and cleared independently. a wups bit may be cleared by writing a 1 to the corresponding bit. the encoding of these bits (wups[1], wups[0]) is as follows: more than one bit may be set indicating that multiple events occurred. the wups field will not be set unless the corresponding event is enabled prior to entering the reduced power state. these bits will set regardless of the values in wake on lan enable (wol_en) and energy-detect enable (ed_en) . if the resume clears remote wake up status (res_clr_wkp_sts) bit is set, wups[1] will clear upon completion of a resume. see the resume clears remote wakeup status (res_clr_wkp_sts) bit for further details. note: it is not valid to simultaneously clear the wups bits and change the contents of the suspend mode (suspend_mode) field. r/wc 00b bits description type default wups[1:0] event 00 no wake-up event detected x1 energy-detect (suspend1) 1x wake on lan (suspend0) / good frame (suspend3) downloaded from: http:///
lan9730/lan9730i ds00001946a-page 132 ? 2012-2015 microchip technology inc. 6.3.9 led general purpose io conf iguration register (led_gpio_cfg) this register configures the external gpio[10:8] pins. in order for a gpio to function as a wake event or interrupt source, it must be configured as an input. gpio pins used to generate wake events mu st also be enabled by the gpio_wake register, see section 6.3.20, "general purpose io wake enable and polarity register (gpio_wake)" . address: 024h size: 32 bits bits description type default 31 led select (led_sel) this bit determines the functionality of external led pins. note: this field is protected by reset protection (rst_protect) . r/w note 6-5 30:26 reserved ro - 25:24 gpio 10 control (gpctl10) the value of this field determines the function of the external gpio10 pin as follows: 00 = gpio10 01 = nspd_led (ethernet speed indicator led) 10 = rxd0 11 = rxd3 note: when enabled as rxd0 or rxd3, the external device pin will reflect the state of the corresponding internal mii signal. this feature is useful as a diagnostic tool. r/w 00b 23:22 reserved ro - 21:20 gpio 9 control (gpctl9) the value of this field determines the function of the external gpio9 pin as fol- lows: 00 = gpio9 01 = note 6-6 10 = rxd1 11 = nphy_rst note: when enabled as rxd1 or nphy_rst, the external device pin will reflect the state of the corresponding internal mii signal. this feature is useful as a diagnostic tool. r/w 00b 19:18 reserved ro - bit value pin name function 0 nspd_led speed indicator nlnka_led link and activity indicator nfdx_led full duplex link indicator note: hardware defaults to activity indicator. software must manipulate to provide full-duplex indication. 1 nspd_led speed indicator nlnka_led link indicator nfdx_led activity indicator downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 133 lan9730/lan9730i note 6-5 the default value for this bit is 0 when no eeprom is present. if an eeprom is present, the default value is the value of the led select bit in the configuration flags of the eeprom. a usb reset or lite reset (lrst) will cause this bit to be restored to the image value last loaded from eeprom, or to be set to 0 if no eeprom is present. note 6-6 determined by the led select (led_sel) setting. note 6-7 the default value depends on the state of the gpio pin. 17:16 gpio 8 control (gpctl8) the value of this field determines the function of the external gpio8 pin as fol- lows: 00 = gpio8 01 = note 6-6 10 = rxd2 11 = crs note: when enabled as rxd2 or crs, the external device pin will reflect the state of the corresponding internal mii signal. this feature is useful as a diagnostic tool. r/w 00b 15:11 reserved ro - 10:8 gpio buffer type (gpbuf[10:8]) when set, the output buffer for the corresponding gpio signal is configured as a push/pull driver. when cleared, the corresponding gpio signal is config- ured as an open-drain driver. bits are assigned as follows: gpbuf8 C bit 8 gpbuf9 C bit 9 gpbuf10 C bit 10 r/w 000b 7 reserved ro - 6:4 gpio direction (gpdir[10:8]) when set, enables the corresponding gpio as an output. when cleared the gpio is enabled as an input. bits are assigned as follows: gpdir8 C bit 4 gpdir9 C bit 5 gpdir10 C bit 6 r/w 000b 3 reserved ro - 2:0 gpio data (gpd[10:8]) when enabled as an output, the value wr itten is reflected on gpion. when read, gpion reflects the current state of the corresponding gpio pin. bits are assigned as follows: gpd8 C bit 0 gpd9 C bit 1 gpd10 C bit 2 r/w note 6-7 bits description type default downloaded from: http:///
lan9730/lan9730i ds00001946a-page 134 ? 2012-2015 microchip technology inc. 6.3.10 general purpose io conf iguration register (gpio_cfg) this register configures gpios 0-7. these gpios ar e not available when using external mii mode. see the phy_sel pin in table 2-4, "miscellaneous pins" . in order for a gpio to function as a wake event or interrup t source, it must be configured as an input. gpios used as wake events must also be enabled by the gpio_wake register, see section 6.3.20, "general purpose io wake enable and polarity regi ster (gpio_wake)" . address: 028h size: 32 bits bits description type default 31:24 gpio enable 0-7 (gpioenn) a '1' sets the associated pin to use the default function. when cleared low, the pin functions as a gpio signal. gpio0 - gpio7 can be used to mirror internal mii signals when not enabled. see the ime bit in section 6.3.5, "hardware configuration register (hw_cfg)" gpioen0 - bit 24 gpioen1 - bit 25 gpioen2 - bit 26 gpioen3 - bit 27 gpioen4 - bit 28 gpioen5 - bit 29 gpioen6 - bit 30 gpioen7 - bit 31 note: these gpios are disabled after a reset. r/w ffh 23:16 gpio buffer type 0-7 (gpiobufn) when set, the output buffer for the corresponding gpio signal is configured as a push/pull driver. when cleared, the corresponding gpio signal is config- ured as an open-drain driver. gpiobuf0 - bit 16 gpiobuf1 - bit 17 gpiobuf2 - bit 18 gpiobuf3 - bit 19 gpiobuf4 - bit 20 gpiobuf5 - bit 21 gpiobuf6 - bit 22 gpiobuf7 - bit 23 r/w 00h 15:8 gpio direction 0-7 (gpiodirn) when set, enables the corresponding gpio as output. when cleared, the gpio is enabled as an input. gpiodir0 - bit 8 gpiodir1 - bit 9 gpiodir2 - bit 10 gpiodir3 - bit 11 gpiodir4 - bit 12 gpiodir5 - bit 13 gpiodir6 - bit 14 gpiodir7 - bit 15 r/w 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 135 lan9730/lan9730i note 6-8 the default value depends on the state of the gpio pin. 7:0 gpio data 0-7 (gpiodn) when enabled as an output, the value wr itten is reflected on gpion. when read, gpiodn reflects the current state of the corresponding gpio pin. gpiod0 - bit 0 gpiod1 - bit 1 gpiod2 - bit 2 gpiod3 - bit 3 gpiod4 - bit 4 gpiod5 - bit 5 gpiod6 - bit 6 gpiod7 - bit 7 r/w note 6-8 bits description type default downloaded from: http:///
lan9730/lan9730i ds00001946a-page 136 ? 2012-2015 microchip technology inc. 6.3.11 automatic flow control co nfiguration register (afc_cfg) this register configures the mechanism that controls both the automatic- and software-initiated transmission of pause frames and back pressure. refer to section 4.5.1, "flow control" for more information on flow control operation. address: 02ch size: 32 bits note: the device will not transmit pause frames or assert back pressure if the transmitter is disabled. bits description type default 31:24 reserved ro - 23:16 automatic flow control high level (afc_hi) specifies, in multiples of 64 bytes, the level at which flow control will trigger. when this limit is reached, the chip w ill apply back pressure or will transmit a pause frame, as programmed in bits [3:0] of this register. during full-duplex operation, only a single pause frame is transmitted when this level is reached. the pause time transmitted in this frame is programmed in the pause time (fcpt) field of the flow control register (flow) , con- tained in the mac csr space. during half-duplex operation, each incoming frame that matches the criteria in bits [3:0] of this register will be jammed for the period set in the back_dur field. r/w 00h 15:8 automatic flow control low level (afc_lo) specifies, in multiples of 64 bytes, the level at which a pause frame is trans- mitted with a pause time setting of zero. when the amount of data in the rx data fifo falls below this level, the pause frame is transmitted. a pause time value of zero instructs the other transmitting device to immediately resume transmission. the zero time pause frame will only be transmitted if the rx data fifo had reached the afc_hi level and a pause frame was sent. a zero pause time frame is sent whenever autom atic flow control in enabled in bits [3:0] of this register. r/w 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 137 lan9730/lan9730i 7:4 back pressure duration (back_dur) this field is used to select the time period for the back pressure duration timer. this field has no function in full-duplex mode. note: back pressure duration is slightly greater in 10 mbs mode. back pressure duration 100 mbps mode: 0h = 5 s 1h = 10 s 2h = 15 s 3h = 25 s 4h = 50 s 5h = 100 s 6h = 150 s 7h = 200 s 8h = 250 s 9h = 300 s ah = 350 s bh = 400 s ch = 450 s dh = 500 s eh = 550 s fh = 600 s 10 mbps mode: 0h = 7.2 s 1h = 12.2 s 2h = 17.2 s 3h = 27.2 s 4h = 52.2 s 5h = 102.2 s 6h = 152.2 s 7h = 202.2 s 8h = 252.2 s 9h = 302.2 s ah = 352.2 s bh = 402.2 s ch = 452.2 s dh = 502.2 s eh = 552.2 s fh = 602.2 s r/w 0h 3 flow control on multicast frame (fcmult) when this bit is set, the device will assert back pressure when the afc level is reached and a multicast frame is received. this field has no function in full- duplex mode. r/w 0b 2 flow control on broadcast frame (fcbrd) when this bit is set, the device will assert back pressure when the afc level is reached and a broadcast frame is received . this field has no function in full- duplex mode. r/w 0b 1 flow control on address decode (fcadd) when this bit is set, the device will assert back pressure when the afc level is reached and a frame addressed to the device is received. this field has no function in full-duplex mode. r/w 0b bits description type default downloaded from: http:///
lan9730/lan9730i ds00001946a-page 138 ? 2012-2015 microchip technology inc. 0 flow control on any frame (fcany) when this bit is set, the device will assert back pressure or transmit a pause frame when the afc level is reached and any frame is received. setting this bit enables full-duplex flow control when the device is operating in full-duplex mode. when this mode is enabled during half-duplex operation, the flow controller does not decode the mac address and will send a pause frame upon receipt of a valid preamble (i.e., immediately at the beginning of the next frame after the rx data fifo level is reached). when this mode is enabled during full-duplex operation, the flow controller will immediately instruct the mac to send a pause frame when the rx data fifo level is reached. the mac will queue the pause frame transmission for the next available window. setting this bit overrides bits [3:1] of this register. r/w 0b bits description type default downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 139 lan9730/lan9730i 6.3.12 eeprom command re gister (e2p_cmd) this register is used to control the read and write operations on the serial eeprom. address: 030h size: 32 bits bits description type default 31 epc busy when a 1 is written into this bit, the operation specified in the epc command field is performed at the specified eepr om address. this bit will remain set until the operation is complete. in the case of a read, the host can read valid data from the e2p data register. the e2p_cmd and e2p_data registers should not be modified until this bit is cleared. in the case where a write is attempted and an eeprom is not pres ent, the epc busy remains busy until the epc time-out occurs. at that time, the busy bit is cleared. note: epc busy will be high immediately following power-up, chip-level, or usb reset. after the eeprom co ntroller has finished reading (or attempts to read) the usb descriptors and ethernet default register values, the epc busy bit is cleared. sc 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 140 ? 2012-2015 microchip technology inc. 30:28 epc command this field is used to issue commands to the eeprom controller. the epc will execute commands when the epc busy bit is set. a new command must not be issued until the previous command completes. this field is encoded as fol- lows: 000 = read 001 = ewds 010 = ewen 011 = write 100 = wral 101 = erase 110 = eral 111 = reload read (read location): this command will ca use a read of the eeprom location pointed to by epc address. the result of the read is available in the e2p_data register. ewds (erase/write disable): after issued, the eeprom will ignore erase and write commands. to re-enable erase/write operations, issue the ewen command. ewen (erase/write enable): enables the eeprom for erase and write operations. the eepr om will allow erase and write operations until the erase/write disable command is sent, or until power is cycled. note: the eeprom device will power-up in the erase/write-disabled state. any erase or write operations will fail until an erase/write enable command is issued. write (write location): if erase/write operations are enabled in the eeprom, this command will cause the cont ents of the e2p_da ta register to be written to the eeprom location selected by the epc address field. wral (write all): if erase/write operations ar e enabled in the eeprom, this command will cause the contents of the e2p_data register to be written to every eeprom memory location. erase (erase location): if erase/write operations are enabled in the eeprom, this command will erase the lo cation selected by the epc address field. eral (erase all): if erase/write operations ar e enabled in the eeprom, this command will initiate a bul k erase of the entire eeprom. reload (data reload): instructs the eeprom controller to reload the data from the eeprom. if a value of a5h is not found in the first address of the eeprom, the eeprom is assumed to be un-programmed and the reload operation will fail. the data loaded bit indicates a successful load of the data. note: a failed reload operation will result in no change to descriptor information or register contents. these items will not be set to default values as a result of the reload failure. r/w 000b 27:11 reserved ro - bits description type default downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 141 lan9730/lan9730i 10 epc time-out if an eeprom operation is performed, and there is no response from the eeprom within 30 ms, the eeprom controller will time-out and return to its idle state. this bit is set when a time-out occurs, indicating that the last opera- tion was unsuccessful. note: if the eedi pin is pulled-high (default if left unconnected), epc commands will not time out if the eeprom device is missing. in this case, the epc busy bit will be cleared as soon as the command sequence is complete. it should also be noted that the erase, eral, write and wral commands are the only epc commands that will time-out if an eeprom device is not present and the eedi signal is pulled low. r/wc 0 9 data loaded when set, this bit indicates that a valid eeprom was found and that the usb and ethernet data programming has completed normally. this bit is set after a successful load of the data after power-up or after a reload command has been completed. r/wc 0 8:0 epc address the 9-bit value in this field is used by the eeprom controller to address a specific memory locati on in the serial eeprom. this is a byte-aligned address. r/w 00h bits description type default downloaded from: http:///
lan9730/lan9730i ds00001946a-page 142 ? 2012-2015 microchip technology inc. 6.3.13 eeprom data register (e2p_data) this register is used in conjunction with the e2p_cmd r egister to perform read and write operations to the serial eeprom. address: 034h size: 32 bits bits description type default 31:8 reserved ro - 7:0 eeprom data value read from or written to the eeprom. r/w 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 143 lan9730/lan9730i 6.3.14 burst cap re gister (burst_cap) this register is used to limit the size of the data burst transmitted by the utx. when more than the amount specified in the burst_cap register is transmitted, the utx will send a zlp. address: 038h size: 32 bits note: this register must be enabled through the section 6.3.5, "hardware configuration register (hw_cfg)" . bits description type default 31:8 reserved ro - 7:0 burst_cap the maximum amount of contiguous data that may be transmitted by the utx before a zlp is sent. this field has units of 512 bytes. note: a value less than or equal to 4 indicates that burst cap enforcement is disabled. in this case, the utx always responds to in tokens with a zlp when the bulk-in empty response (bir) bit in the hardware configuration register (hw_cfg) is deasserted. it will respond with nacks if the bulk-in empty response (bir) bit is set. r/w 00h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 144 ? 2012-2015 microchip technology inc. 6.3.15 data port selec t register (dp_sel) before accessing the internal rams, the testen bit must be set. it is not valid to use the ram data port during run time. the ram test mode select chooses which internal ram to access. the data port ready bit indicates when the data port ram access has been completed. in the case of a read operation, this indicates when the read data has been stored in the dp_data register. address: 040h size: 32 bits bits description type default 31 data port ready (dprdy) 0 = data port is processing a transaction. 1 = data port is ready. ro 1b 30:3 reserved ro - 2:1 ram test select (rsel) selects which ram to access. 00 = fct data ram 01 = eeprom storage ram 10 = tx tli ram 11 = rx tli ram r/w 0b 0 ram test mode enable (testen) put all test accessible rams in test mode. r/w 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 145 lan9730/lan9730i 6.3.16 data port comma nd register (dp_cmd) this register commences the data port access. writing a one to this register will enable a write access, while writing a zero will do a read access. the address and data registers need to be configured appr opriately for the desired read or write operation before accessing this register. address: 044h size: 32 bits bits description type default 31:1 reserved ro - 0 data port write selects operation. writing to this bit initiates the data port access. 0 = read operation 1 = write operation r/w 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 146 ? 2012-2015 microchip technology inc. 6.3.17 data port addr ess register (dp_addr) indicates the address to be used for the data port access. address: 048h size: 32 bits bits description type default 31:15 reserved ro - 14:0 data port address[14:0] note: this quantity specifies a dword address. r/w 0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 147 lan9730/lan9730i 6.3.18 data port data 0 register (dp_data0) the data port data register holds the write data for a write access and the resultant read data for a read access. before reading this register for the result of a read operation, the data port ready bit should be checked. the data port ready bit must indicate the data port is ready. otherwise the read operation is still in progress. address: 04ch size: 32 bits bits description type default 31:0 data port data [31:0] r/w 0000_0000h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 148 ? 2012-2015 microchip technology inc. 6.3.19 data port data 1 register (dp_data1) the data port data register holds the write data for a write access and the resultant read data for a read access. before reading the this register for the result of a read operation, the data port ready bit should be checked. the data port ready bit must indicate the data port is read y. otherwise the read oper ation is still in progress. this register required when accessing the rx tli and tx tli rams. these rams have a width of 37 bits. address: 050h size: 32 bits bits description type default 31:5 reserved ro - 4:0 data port data [36:32] r/w 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 149 lan9730/lan9730i 6.3.20 general purpose io wake enable and polarity register (gpio_wake) this register enables the gpios to function as wake event s for the device when asserted. it also allows the polarity used for a wake event/interrupt to be configured. note 6-9 the default value of this field is loaded from the associated bytes of the eeprom. the high order unused bits of the eeprom are ignored. if no ee prom is present, the default value of each bit in the field is 0. a usb reset or lite reset (lrst) w ill cause this field to be restored to the image value last loaded from eeprom, or will cause the value of each bit to be set to 0 if no eeprom is present. address: 064h size: 32 bits note: gpios must not cause a wake event to the device when not configured as a gpio. bits description type default 31 phy link up enable (phy_linkup_en) setting this bit enables the use of gpio7 to signal a phy link up event when in suspend0 or suspend3 state. in addition to setting this bit, the parame- ters for gpio7 must be set as discussed in section 4.12.2.4, "enabling exter- nal phy link up wake events" in order for signaling to occur. r/w 0b 30:27 reserved ro - 26:16 gpio polarity 0-10 (gpiopoln) 0 = wakeup/interrupt is triggered when gpio is driven low. 1 = wakeup/interrupt is triggered when gpio is driven high. gpiopol0 - bit 16 gpiopol1 - bit 17 gpiopol2 - bit 18 gpiopol3 - bit 19 gpiopol4 - bit 20 gpiopol5 - bit 21 gpiopol6 - bit 22 gpiopol7 - bit 23 gpiopol8 - bit 24 gpiopol9 - bit 25 gpiopol10 - bit 26 r/w 000h 15:11 reserved ro - 10:0 gpio wake 0-10 (gpiowkn) 0 = the gpio can not wake up the device. 1 = the gpio can trigger a wake-up event. gpiowk0 - bit 0 gpiowk1 - bit 1 gpiowk2 - bit 2 gpiowk3 - bit 3 gpiowk4 - bit 4 gpiowk5 - bit 5 gpiowk6 - bit 6 gpiowk7 - bit 7 gpiowk8 - bit 8 gpiowk9 - bit 9 gpiowk10 - bit 10 note: this field is protected by reset protection (rst_protect) . r/w note 6-9 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 150 ? 2012-2015 microchip technology inc. 6.3.21 interrupt endpoint co ntrol register (int_ep_ctl) this register determines which events cause status to be reported by the interrupt endpoint. see section 4.3.1.3, "end- point 3 (interrupt)" for more details. address: 068h size: 32 bits bits description type default 31 interrupt endpoint always on (intep_on) when this bit is set, an interrupt packet will always be sent at the interrupt endpoint interval. 0 = only allow the transmission of an interrupt packet when an interrupt source is enabled and occurs. 1 = always transmit an interrupt packet at the interrupt interval. r/w 0b 30:20 reserved ro - 19 mac reset time out (macrto_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 18 rx fifo has frame enable (rx_fifo_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 17 tx stopped enable (txstop_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 16 rx stopped enable (rxstop_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 15 phy interrupt en able (phy_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 14 transmitter error enable (txe_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 13 tx data fifo underrun interrupt enable (tdfu_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 12 tx data fifo overrun interrupt enable (tdfo_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 151 lan9730/lan9730i 11 rx dropped frame interrupt enable (rxdf_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b 10:0 gpiox interrupt enable (gpiox_en) 0 = this event can not cause an interrupt packet to be issued. 1 = this event can cause an interrupt packet to be issued. r/w 0b bits description type default downloaded from: http:///
lan9730/lan9730i ds00001946a-page 152 ? 2012-2015 microchip technology inc. 6.3.22 bulk-in delay register (bulk_in_dly) address: 06ch size: 32 bits bits description type default 31:16 reserved ro - 15:0 bulk-in delay before sending a short packet, the utx waits the delay specified by this regis- ter. this register has units of 16.667 ns and a default interval of 34.133 s. r/w 800h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 153 lan9730/lan9730i 6.3.23 receive fifo level debug register (dbg_rx_fifo_lvl) address: 070h size: 32 bits bits description type default 31:30 reserved ro - 29:16 rx fifo read level (rxrdlvl) this is a dword count defined as follows: the count is increased by the number of dwords contained in the packet after the entire packet has been written into the fifo. as a packet is read from the fifo, it is decremented each time a dword is read. on rewind, it will increase by the num ber of dwords read out of the fifo. note: rewind case example: on a usb error, whatever was read will be rewound and the packet will be retransmitted to the host. ro 0000h 15:14 reserved ro - 13:0 rx fifo write level (rxwrlvl) this is a dword count defined as follows: as a packet is written into the fifo, it is incremented each time a dword is written. whenever a complete packet has been read from the fifo, it is decreased by the number of dwords contained in the packet. on rewind, it is decreased by the number of dwords of the packet that has currently been transferred into the fifo. note: rewind case example: on an fcs error, whatever was written in the fifo will be rewound out. ro 0000h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 154 ? 2012-2015 microchip technology inc. 6.3.24 receive fifo po inter debug register (dbg_rx_fifo_ptr) this register provides information about the rx fifo read/write pointers. address: 074h size: 32 bits bits description type default 31:29 reserved ro - 28:16 rx fifo read pointer (rxrdptr) current value of rx fifo read pointer (dword address). ro 0000h 15:13 reserved ro - 12:0 rx fifo write pointer (rxwrptr) current value of rx fifo write pointer (dword address). ro 0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 155 lan9730/lan9730i 6.3.25 transmit fifo level debug register (dbg_tx_fifo_lvl) address: 078h size: 32 bits bits description type default 31:28 reserved ro - 27:16 tx fifo read level (txrdlvl) this is a dword count defined as follows: the count is increased by the number of dwords contained in the packet after the entire packet has been written into the fifo. as a packet is read from the fifo, it is decremented each time a dword is read. note: rewinds are not supported. ro 000h 15:12 reserved ro - 11:0 tx fifo write level (txwrlvl) this is a dword count defined as follows: as a packet is written into the fifo, it is incremented each time a dword is written. whenever a complete packet has been read from the fifo, it is decreased by the number of dwords contained in the packet. on rewind, it is decreased by the number of dwords of the packet that has currently been transferred into the fifo. note: write side rewinds are supported, i.e., if a usb packet is received with an error, the packet is rewound out and re-received from the host. ro 000h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 156 ? 2012-2015 microchip technology inc. 6.3.26 transmit fifo pointer d ebug register (dbg_tx_fifo_ptr) this register provides information about the tx fifo read/write pointers. address: 07ch size: 32 bits bits description type default 31:27 reserved ro - 26:16 tx fifo read pointer (txrdptr) current value of tx fifo read pointer (dword address). ro 000h 15:11 reserved ro - 10:0 tx fifo write pointer (txwrptr) current value of tx fifo write pointer (dword address). ro 000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 157 lan9730/lan9730i 6.3.27 hs descriptor attrib utes register (hs_attr) this register sets the length values for hs descriptors that have been loaded into descriptor ram via the data port registers. the hs polling interval is also defined by a fiel d within this register. the descriptor ram images may be used, in conjunction with this register, to facilitate customized operation w hen no eeprom is present. note 6-10 the only legal values are 0 and 0x12h. writing any other values will result in untoward behavior and unexpected results. address: 0a0h size: 32 bits note: if a descriptor does not exist in descriptor ram, its size value must be written as 00h. note: this register only affects system operati on when an eeprom is not present and the eeprom emulation enable (eem) bit indicates descriptor ram and the attributes registers are to be used for descriptor pro- cessing. note: writing to this register when an eeprom is present is prohibited and will result in untoward operation and unexpected results. note: this register is protected by reset protection (rst_protect) . bits description type default 31:24 reserved ro - 23:16 hs polling interval (hs_poll_int) r/w 04h 15:8 hs device descriptor si ze (hs_dev_desc_size) note 6-10 r/w 00h 7:0 hs configuration descriptor size (hs_cfg_desc_size) note 6-10 r/w 00h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 158 ? 2012-2015 microchip technology inc. 6.3.28 fs descriptor attributes register (fs_attr) this register sets the length values for fs descriptors that have been loaded into descriptor ram via the data port reg- isters. the fs polling interval is also defined by a field within this register. the descriptor ram images may be used, in conjunction with this register, to facilitate customized operation w hen no eeprom is present. note 6-11 the only legal values are 0 and 0x12h. writing any other values will result in untoward behavior and unexpected results. address: 0a4h size: 32 bits note: if a descriptor does not exist in descriptor ram, its size value must be written as 00h. note: this register only affects system operati on when an eeprom is not present and the eeprom emulation enable (eem) bit indicates descriptor ram and the attributes registers are to be used for descriptor pro- cessing. note: writing to this register when an eeprom is present is prohibited and will result in untoward operation and unexpected results. note: this register is protected by reset protection (rst_protect) . bits description type default 31:24 reserved ro - 23:16 fs polling interv al (fs_poll_int) r/w 01h 15:8 fs device descriptor si ze (fs_dev_desc_size) note 6-11 r/w 00h 7:0 fs configuration descriptor size (fs_cfg_desc_size) note 6-11 r/w 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 159 lan9730/lan9730i 6.3.29 string descriptor attrib utes register 0 (strng_attr0) this register sets the length values for the named string descriptors that have been loaded into descriptor ram via the data port registers. the descriptor ram images may be used, in conjunction with this register, to facilitate customized operation when no eeprom is present. address: 0a8h size: 32 bits note: if a descriptor does not exist in descriptor ram, its size value must be written as 00h. note: this register only affects system operati on when an eeprom is not present and the eeprom emulation enable (eem) bit indicates descriptor ram and the attributes registers are to be used for descriptor pro- cessing. note: writing to this register when an eeprom is present is prohibited and will result in untoward operation and unexpected results. note: this register is protected by reset protection (rst_protect) . bits description type default 31:24 configuration string descript or size (cfgstr_desc_size) r/w 00h 23:16 serial number string descri ptor size (serstr_desc_size) r/w 00h 15:8 product name string descriptor size (prodstr_desc_size) r/w 00h 7:0 manufacturing string descri ptor size (manuf_desc_size) r/w 00h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 160 ? 2012-2015 microchip technology inc. 6.3.30 string descriptor attrib utes register 1 (strng_attr1) this register sets the length values for the named string descriptors that have been loaded into descriptor ram via the data port registers. the descriptor ram images may be used, in conjunction with this register, to facilitate customized operation when no eeprom is present. address: 0ach size: 32 bits note: if a descriptor does not exist in descriptor ram, its size value must be written as 00h. note: this register only affects system operati on when an eeprom is not present and the eeprom emulation enable (eem) bit indicates descriptor ram and the attributes registers are to be used for descriptor pro- cessing. note: writing to this register when an eeprom is present is prohibited and will result in untoward operation and unexpected results. note: this register is protected by reset protection (rst_protect) . bits description type default 31:8 reserved ro - 7:0 interface string descriptor size (intstr_desc_size) r/w 00h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 161 lan9730/lan9730i 6.3.31 flag attributes register (flag_attr) this register sets the values of el ements of the configurati on flags and pme flags when no eeprom is present and customized operation, using descriptor ram images, is to occu r. this register does not contain configuration flag ele- ments that are components of other registers. those elements will be programmed by the driver software directly prior to initiating customized operation via descriptor ram. note 6-12 the default value depends on the setting of the rmt_wkp strap. address: 0b0h size: 32 bits note: this register only affects system operati on when an eeprom is not present and the eeprom emulation enable (eem) bit indicates descriptor ram and the attributes registers are to be used for descriptor pro- cessing. note: writing to this register when an eeprom is present is prohibited and will result in untoward operation and unexpected results. note: this register is protected by reset protection (rst_protect) . bits description type default 31:18 reserved ro - 17 remote wakeup support (rmt_wkp) refer to remote wakeup support bit in table 4-57, configuration flags for definition. r/w note 6-12 16 power method (pwr_sel) refer to power method bit in table 4-57, configuration flags for definition. r/w 1b 15:8 reserved ro - 7:0 gpio pme flags (pme_flags) refer to table 4-58, gpio pme flags for bit definitions. r/w 00h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 162 ? 2012-2015 microchip technology inc. 6.4 mac control and status registers table 6-4 lists the registers contained in this section. table 6-4: mac control and status register (mcsr) map address register name 100h mac control register (mac_cr) 104h mac address high register (addrh) 108h mac address low register (addrl) 10ch multicast hash table high register (hashh) 110h multicast hash table low register (hashl) 114h mii access register (mii_access) 118h mii data register (mii_data) 11ch flow control register (flow) 120h vlan1 tag register (vlan1) 124h vlan2 tag register (vlan2) 128h wakeup frame filter (wuff) 12ch wakeup control and status register (wucsr) 130h checksum offload engine control register (coe_cr) 134h - 1fch reserved for future use downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 163 lan9730/lan9730i 6.4.1 mac control register (mac_cr) this register establishes the rx and tx operating modes and includes controls for address filtering and packet filtering. address: 100h size: 32 bits bits description type default 31 receive all mode (rxall) when set, all incoming packets will be received and passed on to the address filtering function for processing of the selected filtering mode on the received frame. address filtering then occurs and is reported in receive status. when reset, only frames that pass destination address filtering will be sent to the application. r/w 0b 30:24 reserved ro - 23 disable receive own (rcvown) when set, the mac disables the reception of frames when txen is asserted. the mac blocks the transmitted frame on the receive path. when reset, the mac receives all packets the phy gives, including those transmitted by the mac.this bit should be reset when the full-duplex mode bit is set. r/w 0b 22 reserved ro - 21 loopback operation mode (loopbk) selects the loop back operation modes for the mac. this is only for full- duplex mode. 0 = normal. no feedback 1 = internal through mii in internal loopback mode, the tx frame is received by the internal mii inter- face and sent back to the mac without being sent to the phy. note: when enabling or disabling the loopback mode, it can take up to 10 s for the mode change to occur. the transmitter and receiver must be stopped and disabled when modifying the loopbk bit. the transmitter or receiver should not be enabled within 10 s of modifying the loopbk bit. r/w 0b 20 full duplex mode (fdpx) when set, the mac operates in full-duplex mode, in which it can transmit and receive simultaneously. r/w 0b 19 pass all multicast (mcpas) when set, indicates that all incoming frames with a multicast destination address (first bit in the destination address field is 1) are received. incoming frames with physical address (individual address/unicast) destinations are fil- tered and received only if the address matches the mac address. r/w 0b 18 promiscuous mode (prms) when set, indicates that any incoming frame is received regardless of its des- tination address. r/w 1b 17 inverse filtering (invfilt) when set, the address check function operates in inverse filtering mode. this is valid only during perfect filtering mode. r/w 0b 16 pass bad frames (passbad) when set, all incoming frames that passed address filtering are received, including runt frames, collided frames or truncated frames caused by buffer underrun. r/w 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 164 ? 2012-2015 microchip technology inc. 15 hash only filtering mode (ho) when set, the address check function operates in the imperfect address filter- ing mode both for physical and multicast addresses. r/w 0b 14 reserved ro - 13 hash/perfect filtering mode (hpfilt) when reset (0), the device will implement a perfect address filter on incoming frames, according the address specified in the mac address register. when set (1), the address check function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multi- cast hash table register. if the hash only filtering mode (ho) bit is set (1), then the physical addresses (ia) are imperfect filtered too. if the hash only filtering mode (ho) bit is reset (0), then the ia addresses are perfect address filtered according to the mac address register. r/w 0b 12 late collision control (lcoll) when set, enables retransmission of the collided frame even after the collision period (late collision). when reset, the mac disables frame transmission on a late collision. in any case, the late col lision status is appropriately updated in the transmit packet status. r/w 0b 11 disable broadcast frames (bcast) when set, disables the reception of broadcast frames. when reset, forwards all broadcast frames to the application. note: when wakeup frame detection is enabled via the wakeup frame enable (wuen) bit of the wakeup control and status register (wucsr) , a broadcast wakeup frame will wake up the device despite the state of this bit. r/w 0b 10 disable retry (disrty) when set, the mac attempts only one transmission. when a collision is seen on the bus, the mac ignores the current frame and goes to the next frame and a retry error is reported in the transmit status. when reset, the mac attempts 16 transmissions before signaling a retry error. r/w 0b 9 reserved ro - 8 automatic pad st ripping (padstr) when set, the mac strips the pad field on all incoming frames if the length field is less than 46 bytes. the fcs field is also stripped, since it is computed at the transmitting station based on the data and pad field characters, and is invalid for a received frame that has had the pad characters stripped. receive frames with a 46-byte or greater length field are passed to the application unmodified (fcs is not stripped). when reset, the mac passes all incoming frames to system memory unmodified. r/w 0b bits description type default downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 165 lan9730/lan9730i 7:6 backoff limit (bolmt) the bolmt bits allow the user to set its back-off limit in a relaxed or aggres- sive mode. according to ieee 802.3, the mac has to wait for a random num- ber [r] of slot-times ( note 6-13 ) after it detects a collision, where: (eq.1)0 < r < 2 k the exponent k is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.2)k = min (n, 10) where n is the current number of retries. if a frame has been retried three times, then k = 3 and r = 8 slot-times maxi- mum. if it has been retried 12 times, then k = 10 and r = 1024 slot-times max- imum. an lfsr (linear feedback shift register) 20-bit counter emulates a 20-bit ran- dom number generator, from which r is obtained. once a collis ion is detected, the number of the current retry of the current frame is used to obtain k (eq.2). this value of k translates into the number of bits to use from the lfsr counter. if the value of k is 3, the mac takes the value in the first three bits of the lfsr counter and uses it to count down to zero on every slot-time. this effectively causes the mac to wait eight slot-times. to give the user more flex- ibility, the bolmt value forces the number of bits to be used from the lfsr counter to a predetermined value as in the table below. thus, if the value of k = 10, the mac will look at the bolmt if it is 00, then use the lower ten bits of the lfsr counter for the wait countdown. if the bolmt is 10, t hen it will only use the value in the first fo ur bits for the wait countdown, etc. note 6-13 slot-time = 512 bit times. (s ee ieee 802.3 spec., sections 4.2.3.25 and 4.4.2.1) r/w 00b 5 deferral check (dfchk) when set, enables the deferral check in the mac. the mac will abort the transmission attempt if it has deferred for more than 24,288 bit times. deferral starts when the transmitter is ready to tr ansmit, but is prevented from doing so because the crs is active. defer time is not cumulative. if the transmitter defers for 10,000 bit times, then transmits, collides, ba cks off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. when reset, the deferral check is disabled in the mac and the mac defers indefinitely. r/w 0b 4 reserved ro - 3 transmitter enable (txen) when set, the macs transmitter is enabled and it will transmit frames from the buffer onto the cable. when reset, the macs transmitter is disabled and will not transmit any frames. r/w 0b 2 receiver enable (rxen) when set (1), the macs receiver is enabled and will receive frames from the internal phy. when reset, the macs receiver is disabled and will not receive any frames from the internal phy. r/w 0b bits description type default bolmt value # bits used from lfsr counter 00 10 01 8 10 4 11 1 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 166 ? 2012-2015 microchip technology inc. 1:0 reserved ro - bits description type default downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 167 lan9730/lan9730i 6.4.2 mac address high register (addrh) this register contains the upper 16 bits of the ph ysical address of the mac, where addrh[15:8] is the 6 th octet of the rx frame. address: 104h size: 32 bits note: this register is protected by reset protection (rst_protect) . bits description type default 31:16 reserved ro - 15:0 physical address [47:32] this field contains the upper 16 bits (47:32) of the physical address of the device. r/w ffffh downloaded from: http:///
lan9730/lan9730i ds00001946a-page 168 ? 2012-2015 microchip technology inc. 6.4.3 mac address lo w register (addrl) this register contains the lower 32 bits of the physical addr ess of the mac, where addrl[7:0] is the first octet of the ethernet frame. table 6-5 illustrates the byte ordering of the addrl and addrh re gisters with respect to the reception of the ethernet physical address. as an example, if the desired ethernet physical address is 12-34-56-78-9a-bc, the addrl and addrh registers would be programmed as shown in figure 6-1 . address: 108h size: 32 bits note: this register is protected by reset protection (rst_protect) . bits description type default 31:0 physical address [31:0] this field contains the lower 32 bits (31:0) of the physical address of this mac device. r/w ffff_ffffh table 6-5: addrl, addrh byte ordering addrl, addrh order of reception on ethernet addrl[7:0] 1 st addrl[15:8] 2 nd addrl[23:16] 3 rd addrl[31:24] 4 th addrh[7:0] 5 th addrh[15:8] 6 th figure 6-1: example addrl, addrh address ordering 0x12 0 7 0x34 8 15 0x56 16 23 0x78 24 31 addrl 0x9a 0 7 0xbc 8 15 addrh xx 16 23 xx 24 31 downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 169 lan9730/lan9730i 6.4.4 multicast hash tabl e high register (hashh) the 64-bit multicast table is used for group address filtering. for hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the has h table. the most significant bit determines the register to be used (high/low), while the other five bits determine the bit within the register. a value of 00000 selects bit 0 of the multicast hash table low register and a value of 11111 sel ects the bit 31 of the multicast hash table high register. if the corresponding bit is 1, then the multicast frame is a ccepted. otherwise, it is rejected. if the pass all multicast ( mcpas) bit is set (1), then all multicast frames are accepted regardless of the multicast hash values. the multicast hash table high register contains the higher 32 bits of the hash table and the multicast hash table low register contains the lower 32 bits of the hash table. address: 10ch size: 32 bits bits description type default 31:0 upper 32 bits of the 64-bit hash table r/w 0000_0000h downloaded from: http:///
lan9730/lan9730i ds00001946a-page 170 ? 2012-2015 microchip technology inc. 6.4.5 multicast hash t able low register (hashl) this register defines the lower 32-bits of the multicast hash table. refer to section 6.4.4, "multicast hash table high register (hashh)" for further details. address: 110h size: 32 bits bits description type default 31:0 lower 32 bits of the 64-bit hash table r/w 0000_0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 171 lan9730/lan9730i 6.4.6 mii access register (mii_access) this register is used to control the management cycles to the internal phy. address: 114h size: 32 bits bits description type default 31:16 reserved ro - 15:11 phy address for every access to this register, this field must be set to 00001b. r/w 00000b 10:6 mii register index (miirinda) these bits select the desired mii register in the phy. r/w 00000b 5:2 reserved ro - 1 mii write (miiwnr) setting this bit tells the phy that this will be a write operation using the mii data register. if this bit is not set, this will be a read operation, packing the data in the mii data register. r/w 0b 0 mii busy (miibzy) this bit must be polled to determine when the mii register access is complete. this bit must read a logical 0 before writing to this register or to the mii data register. the lan driver software must set (1) this bit in order for the host to read or write any of the mii phy registers. during an mii register access, this bit will be set, signifying a read or write access is in progress. the mii data register must be kept valid until the mac clears this bit during a phy write operation. the mii data register is invalid until the mac has cleared this bit during a phy read operation. sc 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 172 ? 2012-2015 microchip technology inc. 6.4.7 mii data register (mii_data) this register contains either the data to be written to the phy register specified in the mii access register, or the read data from the phy register whose index is specified in the mii access register. refer to section 6.4.6, "mii access reg- ister (mii_access)" for further details. address: 118h size: 32 bits note: the miibzy bit in the mii_access register must be cleared when writing to this register. bits description type default 31:16 reserved ro - 15:0 mii data this contains the 16-bit value read from the phy read operation or the 16-bit data value to be written to the phy before an mii write operation. r/w 0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 173 lan9730/lan9730i 6.4.8 flow control register (flow) this register is used to control the generation and recept ion of the control frames by the macs flow control block. before writing to this register, the application has to make sure that the busy bit is not set. address: 11ch size: 32 bits bits description type default 31:16 pause time (fcpt) this field indicates the value to be used in the pause time field in the control frame. r/w 0000h 15:3 reserved ro - 2 pass control frames (fcpass) when set, the mac sets the packet filter bit in the receive packet status to indicate to the application that a valid pause frame has been received. the application must accept or discard a received frame based on the packet filter control bit. the mac receives, decodes and performs the pause function when a valid pause frame is received in full-duplex mode and when flow con- trol is enabled (fcen bit set). when reset, the mac resets the packet filter bit in the receive packet status. the mac always passes the data of all frames it receives (including flow con- trol frames) to the application. frames that do not pass address filtering, as well as frames with errors, are passed to the application. the application must discard or retain the received frames data based on the received frames status field. filtering modes (promi scuous mode, for example) take prece- dence over the fcpass bit. r/w 0b 1 flow control enable (fcen) when set, enables the mac flow control function. the mac decodes all incoming frames for control frames; if it receives a valid control frame (pause command), it disables the transmitter for a specified time (decoded pause time x slot time). when reset, the mac flow control function is disabled; the mac does not decode frames for control frames. note: flow control is applicable when the mac is set in full-duplex mode. in half-duplex mode, this bit enables the back pressure function to control the flow of received frames to the mac. r/w 0b 0 flow control busy (fcbsy) this bit is set high whenever a pause frame or back pressure is being trans- mitted. this bit should read logical 0 before writing to the flow control (flow) register. during a transfer of control frame, this bit continues to be set, signifying that a frame transmission is in progress. after the pause con- trol frame's transmission is complete, the mac resets to 0. note: when writing this register th e fcbsy bit must always be zero. note: applications must always write a zero to this bit. r/w 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 174 ? 2012-2015 microchip technology inc. 6.4.9 vlan1 tag register (vlan1) this register contains the vlan tag field to identify vlan1 frames. for vlan frames, the legal frame length is increased from 1518 bytes to 1522 bytes. the rxcoe also uses this register to determine the protocol value to use to indicate the existence of a vlan tag. when using the rxcoe, this value may only be changed if the rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the mac is disabled and the tli is empty. address: 120h size: 32 bits bits description type default 31:16 reserved ro - 15:0 vlan1 tag identifier (vti1) this contains the vlan tag field to identify the vlan1 frames. this field is compared with the 13 th and 14 th bytes of the incoming frames for vlan1 frame detection. r/w ffffh downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 175 lan9730/lan9730i 6.4.10 vlan2 tag register (vlan2) this register contains the vlan tag field to identify vlan2 frames. for vlan frames the legal frame length is increased from 1518 bytes to 1522 bytes. address: 124h size: 32 bits bits description type default 31:16 reserved ro - 15:0 vlan2 tag identifier (vti2) this contains the vlan tag field to identify the vlan2 frames. this field is compared with the 13 th and 14 th bytes of the incoming frames for vlan2 frame detection. r/w ffffh downloaded from: http:///
lan9730/lan9730i ds00001946a-page 176 ? 2012-2015 microchip technology inc. 6.4.11 wakeup frame filter (wuff) this register is used to configure the wakeup frame filter. address: 128h size: 32 bits bits description type default 31:0 wakeup frame filter (wff) the wakeup frame filter is configured through this register using an indexing mechanism. following a reset, the mac loads the first value written to this location to the first dword in the wak eup frame filter (filter 0 byte mask 0). the second value written to this location is loaded to the second dword in the wakeup frame filter (filter 0 byte mask 1) and so on. once 40 dwords (8 filters) have been writte n, the internal pointer will once again point to the first entry and the filter entries can be modified in the same manner. similarly, 40 dwords (8 filters) can be read sequentially to obtain the values stored in the wff. refer to section 4.5.5, "wakeup frame detection" for further infor- mation concerning the wakeup frame filter. note: this register should be read and written using 40 (8 filters) consecutive dword operations. failure to read or write the entire contents of the wff may cause the internal read/write pointers to be left in a position other than pointing to the first entry. a mechanism for resetting the internal pointers to the beginning of the wff is available via the wff pointer reset (wff_ptr_rst) bit of the wakeup control and status register (wucsr) . this mechanism enables the application program to re-synchronize with the internal wff pointers if it has not previously read/written the complete contents of the wff. r/w 0000_0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 177 lan9730/lan9730i 6.4.12 wakeup contro l and status register (wucsr) this register contains data pertaining to the macs remote wakeup status and capabilities. address: 12ch size: 32 bits bits description type default 31 wff pointer reset (wff_ptr_rst) this self-clearing bit resets the wakeup frame filter (wff) internal read and write pointers to the beginning of the wff. sc 0b 30:10 reserved ro - 9 global unicast wakeup enable (guen) when set, the mac wakes up from power-saving mode on receipt of a global unicast frame. a global unicast frame has the mac address [0] bit set to 0. note: the wakeup frame enable (wuen) bit of this register must also be set to enable wakeup. r/w 0b 8 reserved ro - 7 perfect da frame received (pfda_fr) the mac sets this bit upon receiving a valid frame with a destination address that matches the physical address. this bit is automatically cleared at the completion of a resume sequence if resume clears remote wake up status (res_clr_wkp_sts) is set. r/wc 0b 6 remote wakeup frame received (wufr) the mac sets this bit upon receiving a valid remote wakeup frame. this bit is automatically cleared at the completion of a resume sequence if resume clears remote wake up status (res_clr_wkp_sts) is set. r/wc 0b 5 magic packet received (mpr) the mac sets this bit upon receiving a valid magic packet. this bit is automatically cleared at the completion of a resume sequence if resume clears remote wake up status (res_clr_wkp_sts) is set. r/wc 0b 4 broadcast frame received (bcast_fr) the mac sets this bit upon receiving a valid broadcast frame. this bit is automatically cleared at the completion of a resume sequence if resume clears remote wake up status (res_clr_wkp_sts) is set. r/wc 0b 3 perfect da wakeup enable (pfda_en) when set, remote wakeup mode is enabled and the mac is capable of waking up on receipt of a frame with a destination address that matches the physical address of the device. the physical address is stored in the mac address high register (addrh) and mac address low register (addrl) . r/w 0b 2 wakeup frame enable (wuen) when set, remote wakeup mode is enabled and the mac is capable of detect- ing wakeup frames as programmed in the wakeup frame filter. r/w 0b 1 magic packet enable (mpen) when set, magic packet wakeup mode is enabled. r/w 0b 0 broadcast wakeup enable (bcast_en) when set, remote wakeup mode is enabled and the mac is capable of waking up from a broadcast frame. r/w 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 178 ? 2012-2015 microchip technology inc. 6.4.13 checksum offload engine control register (coe_cr) this register controls the rx and tx checksum offload engines . address: 130h size: 32 bits bits description type default 31:17 reserved ro - 16 tx checksum offload engi ne enable (tx_coe_en) tx_coe_en may only be changed if the tx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the mac is dis- abled and the tli is empty. 0 = the txcoe is bypassed. 1 = the txcoe is enabled. r/w 0b 15:2 reserved ro - 1 rx checksum offload engine mode (rx_coe_mode) this register indicates whether the coe will check for vlan tags or a snap header prior to beginning its checksum calculation. in its default mode, the calculation will always begin 14 bytes into the frame. rx_coe_mode may only be changed if the rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the mac is disabled and the tli is empty. 0 = begin checksum calculation after first 14 bytes of ethernet frame. 1 = begin checksum calculation at start of l3 packet by adjusting for vlan tags and/or snap header. r/w 0b 0 rx checksum offload engine enable (rx_coe_en) rx_coe_en may only be changed if the rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the mac is disabled and the tli is empty. 0 = the rxcoe is bypassed. 1 = the rxcoe is enabled. r/w 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 179 lan9730/lan9730i 6.5 phy registers the phy registers are not memory mapped. these registers are accessed indirectly through the mac via the mii access register (mii_access) and mii access register (mii_access) . an index is used to access individual phy registers. phy register indexes are shown in table 6-6, "phy control and status register" below. note: the nasr ( not affected by software reset) designation is only applicable when bit 15 of the phy basic control register (reset) is set. table 6-6: phy control and status register index (in decimal) register name 0 basic control register 1 basic status register 2 phy identifier 1 register 3 phy identifier 2 register 4 auto negotiation advertisement register 5 auto negotiation link partner ability register 6 auto negotiation expansion register 16 edpd nlp/crossover timeregister 17 mode control/status register 18 special modes register 26 symbol error counter register 27 special control/status indications register 29 interrupt source flag register 30 interrupt mask register 31 phy special control/status register downloaded from: http:///
lan9730/lan9730i ds00001946a-page 180 ? 2012-2015 microchip technology inc. 6.5.1 basic control register index (in decimal): 0 size: 16 bits bits description type default 15 phy soft reset 1 = phy software reset. bit is self-clearing. when setting this bit do not set other bits in this register. note: the phy will be in the normal mode after a phy software reset. r/w sc 0b 14 loopback 0 = normal operation 1 = loopback mode r/w 0b 13 speed select 0 = 10 mbps 1 = 100 mbps note: ignored if auto negotiation is enabled (0.12 = 1). r/w 1b 12 auto-negotiation enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides 0.13 and 0.8) r/w 1b 11 power down 0 = normal operation 1 = general power down mode note: the auto-negotiation enable must be cleared before setting the power down. r/w 0b 10 reserved ro - 9 restart auto-negotiate 0 = normal operation 1 = restart auto-negotiate process note: bit is self-clearing. r/w sc 0b 8 duplex mode 0 = half duplex 1 = full duplex note: ignored if auto negotiation is enabled (0.12 = 1). r/w 0b 7 collision test 0 = disable col test 1 = enable col test r/w 0b 6:0 reserved ro - downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 181 lan9730/lan9730i 6.5.2 basic status register index (in decimal): 1 size: 16 bits bits description type default 15 100base-t4 0 = no t4 ability 1 = t4 able ro 0b 14 100base-tx full duplex 0 = no tx full-duplex ability 1 = tx with full-duplex ability ro 1b 13 100base-tx half duplex 0 = no tx half-duplex ability 1 = tx with half-duplex ability ro 1b 12 10base-t full duplex 0 = no 10 mbps with full-duplex ability 1 = 10 mbps with full-duplex ability ro 1b 11 10base-t half duplex 0 = no 10 mbps with half-duplex ability 1 = 10 mbps with half-duplex ability ro 1b 10:6 reserved ro - 5 auto-negotiate complete 0 = auto-negotiate process not completed 1 = auto-negotiate process completed ro 0b 4 remote fault 1 = remote fault condition detected 0 = no remote fault ro/lh 0b 3 auto-negotiate ability 0 = unable to perform auto-negotiation function 1 = able to perform auto-negotiation function ro 1b 2 link status 0 = link is down 1 = link is up ro/ll 0b 1 jabber detect 0 = no jabber condition detected 1 = jabber condition detected ro/lh 0b 0 extended capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers ro 1b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 182 ? 2012-2015 microchip technology inc. 6.5.3 phy identi fier 1 register index (in decimal): 2 size: 16 bits bits description type default 15:0 phy id number assigned to the 3 rd through 18 th bits of the organizationally unique identifier (oui), respectively. r/w 0007h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 183 lan9730/lan9730i 6.5.4 phy identi fier 2 register index (in decimal): 3 size: 16 bits bits description type default 15:10 phy id number assigned to the 19 th through 24 th bits of the oui. r/w c101h 9:4 model number six-bit manufacturers model number. r/w 3:0 revision number four-bit manufacturers revision number. r/w note: the default value of the revision number field may vary dependent on the silicon revision number. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 184 ? 2012-2015 microchip technology inc. 6.5.5 auto negotiation advertisement register index (in decimal): 4 size: 16 bits bits description type default 15:14 reserved ro - 13 remote fault 0 = no remote fault 1 = remote fault detected r/w 0b 12 reserved ro - 11:10 pause operation 00 = no pause 01 = symmetric pause 10 = asymmetric pause toward link partner 11 = advertise support for both symmetric pause and asymmetric pause toward local device note: when both symmetric pause and asymmetric pause are set, the device will only be configured to, at most, one of the two settings upon autonegotiation completion. r/w 00b 9 reserved ro - 8 100base-tx full duplex 0 = no tx full-duplex ability 1 = tx with full-duplex ability r/w 1b 7 100base-tx 0 = no tx ability 1 = tx able r/w 1b 6 10base-t full duplex 0 = no 10 mbps with full-duplex ability 1 = 10 mbps with full-duplex ability r/w 1b 5 10base-t 0 = no 10 mbps ability 1 = 10 mbps able r/w 1b 4:0 selector field 00001 = ieee 802.3 r/w 00001b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 185 lan9730/lan9730i 6.5.6 auto negotiation link partner ability register index (in decimal): 5 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable note: next page ability is not supported. ro 0b 14 acknowledge 0 = link code word not yet received 1 = link code word received from partner ro 0b 13 remote fault 0 = no remote fault 1 = remote fault detected ro 0b 12 reserved ro - 11:10 pause operation 00 = no pause supported by partner station 01 = symmetric pause supported by partner station 10 = asymmetric pause supported by partner station 11 = both symmetric pause and asy mmetric pause supported by partner station ro 00b 9 100base-t4 0 = no t4 ability 1 = t4 able note: this device does not support t4 ability. ro 0b 8 100base-tx full duplex 0 = no tx full-duplex ability 1 = tx with full-duplex ability ro 0b 7 100base-tx 0 = no tx ability 1 = tx able ro 0b 6 10base-t full duplex 0 = no 10 mbps with full-duplex ability 1 = 10 mbps with full-duplex ability ro 0b 5 10base-t 0 = no 10 mbps ability 1 = 10 mbps able ro 0b 4:0 selector field 00001 = ieee 802.3 ro 00001b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 186 ? 2012-2015 microchip technology inc. 6.5.7 auto negotiation expansion register index (in decimal): 6 size: 16 bits bits description type default 15:5 reserved ro - 4 parallel detection fault 0 = no fault detected by parallel detection logic. 1 = fault detected by parallel detection logic. ro/lh 0b 3 link partner next page able 0 = link partner does not have next page ability. 1 = link partner has next page ability. ro 0b 2 next page able 0 = local device does not have next page ability. 1 = local device has next page ability. note: next page ability is not supported. ro 0b 1 page received 0 = new page not yet received 1 = new page received ro/lh 0b 0 link partner auto-negotiation able 0 = link partner does not have auto-negotiation ability. 1 = link partner has auto-negotiation ability. ro 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 187 lan9730/lan9730i 6.5.8 edpd nlp/crossover timeregister index (in decimal): 16 size: 16 bits bits description type default 15 edpd tx nlp enable when in energy detect power-down (edpd) mode ( edpwrdown =1), this bit enables the transmission of single tx nlps at the interval defined by the edpd tx nlp interval timer select field. 0 = tx nlp disabled 1 = tx nlp enabled when in edpd mode r/w nasr 0b 14:13 edpd tx nlp interval timer select when in energy detect power-down (edpd) mode ( edpwrdown =1) and edpd tx nlp enable is 1, this field defines the interval used to send single tx nlps. 00 = 1 second (default) 01 = 768 ms 10 = 512 ms 11 = 256 ms r/w nasr 00b 12 edpd rx single nlp wake enable when in energy detect power-down (edpd) mode ( edpwrdown =1), this bit enables waking the phy on reception of a single rx nlp. 0 = rx nlp wake disabled 1 = tx nlp wake enabled when in edpd mode r/w nasr 0b 11:10 edpd rx nlp max interval detect select when in energy detect power-down (edpd) mode ( edpwrdown =1) and edpd rx single nlp wake enable is 0, this field defines the maximum inter- val for detecting two rx nlps to wake from edpd mode. 00 = 64 ms (default) 01 = 256 ms 10 = 512 ms 11 = 1 second r/w nasr 00b 9:2 reserved ro - 1 edpd extend crossover when in energy detect power-down (edpd) mode ( edpwrdown = 1), set- ting this bit to 1 extends the crossover time by 2976 ms. 0 = crossover time extension disabled 1 = crossover time extension enabled (2976 ms) r/w nasr 0b 0 extend manual 10/100 auto-mdix crossover time when auto-midx is enabled and the phy is in manual 10base-t or 100base-tx mode, setting this bit to 1 extends the crossover time by 1984 ms to allow linking to an auto-negotiation link partner phy. 0 = crossover time extension disabled 1 = crossover time extension enabled (1984 ms) r/w nasr 0b downloaded from: http:///
lan9730/lan9730i ds00001946a-page 188 ? 2012-2015 microchip technology inc. 6.5.9 mode control/ status register index (in decimal): 17 size: 16 bits bits description type default 15:14 reserved ro - 13 edpwrdown enable the energy detect power-down mode: 0 = energy detect power-down is disabled 1 = energy detect power-down is enabled note: it is recommended to enable auto-negotiation before enabling edpd mode. note: when in edpd mode, the devices nlp characteristics can be modified via the edpd nlp/crossover timeregister . r/w 0b 12:2 reserved ro - 1 energyon indicates whether energy is detected. this bit goes to a 0 if no valid energy is detected within 256 ms. it is reset to 1 by a hardware reset and unaffected by a software reset. ro 1b 0 reserved r/w 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 189 lan9730/lan9730i 6.5.10 special modes register index (in decimal): 18 size: 16 bits bits description type default 15:8 reserved ro - 7:5 mode phy mode of operation. refer to table 6-7 for more details. r/w nasr 111b 4:0 phyadd phy address. the phy address is used for the smi address. r/w nasr 00001b table 6-7: mode control mode mode definitions default register bit values register 0 register 4 [13,12,8] [8,7,6,5] 000b 10base-t half duplex. auto -negotiation disabled. 000 n/a 001b 10base-t full duplex. auto-negotiation disabled. 001 n/a 010b 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 100 n/a 011b 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 101 n/a 100b 100base-tx half duplex is advertised. auto-negoti- ation enabled. crs is active during transmit & receive. 110 0100 101b repeater mode. auto-negotiation enabled. 100base-tx half duplex is advertised. crs is active during receive. 110 0100 110b reserved - do not set the device in this mode. n/a n/a 111b all capable. auto-negotiation enabled. x1x 1111 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 190 ? 2012-2015 microchip technology inc. 6.5.11 symbol error counter register index (in decimal): 26 size: 16 bits bits description type default 15:0 symbol error counter (sym_err_cnt) this 100base-tx receive r-based error counter increments when an invalid code symbol is received, including idle symbols. the counter is incremented only once per packet, even when the received packet contains more than one symbol error. this field counts up to 65,536 and rolls over to 0 if incremented beyond its maximum value. note: this register is cleared on reset, but is not cleared by reading the register. it does not increment in 10base-t mode. ro 0000h downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 191 lan9730/lan9730i 6.5.12 special control/stat us indications register index (in decimal): 27 size: 16 bits bits description type default 15 override automdix_en strap 0 = automdix_en configuration strap enables or disables hp auto mdix 1 = override automdix_en configuration strap. phy register 27.14 and 27.13 determine mdix function r/w nasr 0b 14 auto-mdix enable only effective when 27.15 = 1, otherwise ignored. 0 = disable auto-mdix. 27.13 determi nes normal or reversed connection. 1 = enable auto-mdix. 27.13 must be set to 0. r/w nasr 0b 13 auto-mdix state only effective when 27.15 = 1, otherwise ignored. when 27.14 = 0 (manually set mdix state): 0 = no crossover (tpo = output, tpi = input) 1 = crossover (tpo = input, tpi = output) when 27.14 = 1 (automatic mdix) this bit must be set to 0. do not use the combination 27.15=1, 27.14=1, 27.13=1. r/w nasr 0b 12:5 reserved ro - 4 xpol polarity state of the 10base-t: 0 = normal polarity 1 = reversed polarity ro 0b 3:0 reserved ro - downloaded from: http:///
lan9730/lan9730i ds00001946a-page 192 ? 2012-2015 microchip technology inc. 6.5.13 interrupt source flag register index (in decimal): 29 size: 16 bits bits description type default 15:8 reserved ro - 7 int7 0 = not source of interrupt 1 = energyon generated ro/lh 0b 6 int6 0 = not source of interrupt 1 = auto-negotiation complete ro/lh 0b 5 int5 0 = not source of interrupt 1 = remote fault detected ro/lh 0b 4 int4 0 = not source of interrupt 1 = link down (link status negated) ro/lh 0b 3 int3 0 = not source of interrupt 1 = auto-negotiation lp acknowledge ro/lh 0b 2 int2 0 = not source of interrupt 1 = parallel detection fault ro/lh 0b 1 int1 0 = not source of interrupt 1 = auto-negotiation page received ro/lh 0b 0 reserved ro 0b downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 193 lan9730/lan9730i 6.5.14 interrupt mask register index (in decimal): 30 size: 16 bits bits description type default 15:8 reserved ro - 7:1 mask bits these bits mask the corresponding interrupts in the interrupt source flag register . 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0000000b 0 reserved ro - downloaded from: http:///
lan9730/lan9730i ds00001946a-page 194 ? 2012-2015 microchip technology inc. 6.5.15 phy special control/status register index (in decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 autodone auto-negotiation done indication: 0 = auto-negotiation is not done or disabled (or not active). 1 = auto-negotiation is done. ro 0 11:5 reserved - write as 0000010b, ignore on read. r/w 0000010b 4:2 speed indication hcdspeed value: 001 = 10 mbps half-duplex 101 = 10 mbps full-duplex 010 = 100base-tx half-duplex 110 = 100base-tx full-duplex ro xxxb 1:0 reserved ro - downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 195 lan9730/lan9730i 7.0 operational characteristics 7.1 absolute maximum ratings* +3.3 v supply voltage ( vdd33io, vdd33a ) note 7-1 .................................................................................... 0 v to +3.6 v +1.2 v supply voltage ( vdd12core, vdd12pll, vdd12usbpll, vdd12a ) note 7-1 .................................... 0 v to +1.5 v positive voltage on input signal pins, with respect to ground note 7-2 ................................................. vdd33io + 2.0 v negative voltage on input signal pins, with respect to ground note 7-3 ..................................................................-0.5 v positive voltage on xi, with respect to ground ......................................................................... ........ ........... vdd12core storage temperature .................................................................................................... ........ ..................-55 o c to +150 o c lead temperature range ........................................................................................... refer to jedec spec. j-std-020 hbm esd performance ............................................................................................................ ............ .jedec class 3a note 7-1 when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested to use a clamp circuit. note 7-2 this rating does not apply to the following pins: xi, xo, exres, usbrbias, hsic_strobe, hsic_data. note 7-3 this rating does not apply to the following pins: exres, usbrbias, hsic_strobe, hsic_data. * stresses exceeding those listed in this section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 7.2, "operating conditions**" , section 7.4, "dc specifications" , or any other applicable section of this specif ication is not implied. note, device signals are not 5 volt tolerant unless specified otherwise. 7.2 operating conditions** +3.3 v supply voltage ( vdd33io, vdd33a ) ................................................................................................ +3.3 v +/-10% +1.2 v supply voltage ( vdd12core, vdd12pll, vdd12usbpll, vdd12a ) ........................................... +1.2 v +10%/-5% ambient operating temperature in still air (t a )................................................................................................. note 7-4 note 7-4 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. ** proper operation of the device is guaranteed only within the ranges specified in this section. downloaded from: http:///
lan9730/lan9730i ds00001946a-page 196 ? 2012-2015 microchip technology inc. 7.3 power consumption this section details the power consumption of the device as measured during various mo des of operation. power con- sumption values are provided for both the device-only, and for the device plus ethernet components. power dissipation is determined by temperature, supply voltage and external source/sink requirements. 7.3.1 power consumption - internal regulator disabled 7.3.1.1 suspend0 - intern al regulator disabled 7.3.1.2 suspend1 - intern al regulator disabled 7.3.1.3 suspend2 - intern al regulator disabled note: all current consumption and power dissipation valu es were measured with vdd33io and vdd33a equal to 3.3 v. table 7-1: power consumption/dissipation - suspend0 - int. reg. disabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 30 ma supply current (vdd12core, vdd12usbpll, vdd12a, vdd12pll) (device only) 19 ma power dissipation (device only) 121 mw power dissipation (device and ethernet components) 255 mw table 7-2: power consumption/dissipation - suspend1 - int. reg. disabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 5 ma supply current (vdd12core, vdd12usbpll, vdd12a, vdd12pll) (device only) 3m a power dissipation (device only) 19 mw power dissipation (device and ethernet components) 19 mw table 7-3: power consumption/dissipation - suspend2 - int. reg. disabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 1 ma supply current (vdd12core, vdd12usbpll, vdd12a, vdd12pll) (device only) 1m a power dissipation (device only) 5 mw power dissipation (device and ethernet components) 6 mw downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 197 lan9730/lan9730i 7.3.1.4 suspend3 - intern al regulator disabled 7.3.1.5 operational - internal regulator disabled 7.3.2 power consumption - internal regulator enabled 7.3.2.1 suspend0 - internal regulator enabled 7.3.2.2 suspend1 - internal regulator enabled table 7-4: power consumption/dissipation - suspend3 - int. reg. disabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 30 ma supply current (vdd12core, vdd12usbpll, vdd12a, vdd12pll) (device only) 37 ma power dissipation (device only) 145 mw power dissipation (device and ethernet components) 279 mw table 7-5: operational power consumption/dissipation - int. reg. disabled parameter min typ. max. unit 100base-tx full duplex (hsic) supply current (vdd33io, vdd33a) (device only) 32 ma supply current (vdd12core, vdd12usbpll, vdd12a, vdd12pll) (device only) 42 ma power dissipation (device only) 156 mw power dissipation (device and ethernet components) 292 mw 10base-t full duplex (hsic) supply current (vdd33io, vdd33a) (device only) 12 ma supply current (vdd12core, vdd12usbpll, vdd12a, vdd12pll) (device only) 32 ma power dissipation (device only) 77 mw power dissipation (device and ethernet components) 407 mw table 7-6: power consumption/dissipation - suspend0 - int. reg. enabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 50 ma power dissipation (device only) 164 mw power dissipation (device and ethernet components) 296 mw table 7-7: power consumption/dissipation - suspend1 - int. reg. enabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 8 ma power dissipation (device only) 26 mw power dissipation (device and ethernet components) 26 mw downloaded from: http:///
lan9730/lan9730i ds00001946a-page 198 ? 2012-2015 microchip technology inc. 7.3.2.3 suspend2 - internal regulator enabled 7.3.2.4 suspend3 - internal regulator enabled 7.3.2.5 operational - internal regulator enabled table 7-8: power consumption/dissipation - suspend2 - int. reg. enabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 3 ma power dissipation (device only) 9 mw power dissipation (device and ethernet components) 10 mw table 7-9: power consumption/dissipation - suspend3 - int. reg. enabled parameter min typ. max. unit supply current (vdd33io, vdd33a) (device only) 69 ma power dissipation (device only) 228 mw power dissipation (device and ethernet components) 361 mw table 7-10: operational power consumption/dissipation - int. reg. enabled parameter min typ. max. unit 100base-tx full duplex (hsic) supply current (vdd33io, vdd33a) (device only) 71 ma power dissipation (device only) 235 mw power dissipation (device and ethernet components) 370 mw 10base-t full duplex (hsic) supply current (vdd33io, vdd33a) (device only) 44 ma power dissipation (device only) 146 mw power dissipation (device and ethernet components) 478 mw downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 199 lan9730/lan9730i 7.4 dc specifications table 7-11: i/o buffer characteristics parameter symbol min. typ. max. unit note is type input buffer low input level high input level negative-going threshold positive-going threshold schmitttrigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vdd33io) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 1.01 1.39 336 -10 1.19 1.59 399 3.6 1.39 1.8 485 10 3 vv v v mv a pf schmitt trigger schmitt trigger note 7-5 o8 type buffers low output level high output level v ol v oh vdd33io - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma od8 type buffer low output level v ol 0.4 v i ol = 8 ma o12 type buffers low output level high output level v ol v oh vdd33io - 0.4 0.4 v v i ol = 12 ma i oh = -12 ma od12 type buffer low output level v ol 0.4 v i ol = 12 ma hsic type buffers low input level high input level low output level high output level i/o pad drive strength (50driver_en = vss) i/o pad drive strength (50driver_en = +3.3v) input leakage (v in = vss or vdd33io) input capacitance v il v ih v ol v oh o d o d i ih c in -0.3 0.65* vdd12a 0.75*vdd12a 38 47.5 -10 4050 0.35* vdd12a vdd12a + 0.3 0.25*vdd12a 42 52.5 10 4 vv v v ohmohm a pf downloaded from: http:///
lan9730/lan9730i ds00001946a-page 200 ? 2012-2015 microchip technology inc. note 7-5 this specification applies to all inputs and tri-stat ed bi-directional pins. internal pull-down and pull-up resistors add +/- 50 a per-pin (typical). note 7-6 xi can optionally be driven from a 25 mhz single-ended clock oscillator. note 7-7 measured at line side of transformer, line replaced by 100 ? (+/-1%) resistor. note 7-8 offset from 16 ns pulse width at 50% of pulse peak. note 7-9 measured differentially. note 7-10 min/max. voltages guaranteed as measured with 100 ? resistive load. iclk type buffer (xi input) low input level high input level v ili v ihi 0.8 0.35 v v note 7-6 table 7-12: 100base-tx transceiver characteristics parameter symbol min. typ. max. unit note peak differential output voltage high v pph 950 - 1050 mvpk note 7-7 peak differential output voltage low v ppl -950 - -1050 mvpk note 7-7 signal amplitude symmetry v ss 98 - 102 % note 7-7 signal rise and fall time t rf 3.0 - 5.0 ns note 7-7 rise and fall symmetry t rfs --0 . 5n s note 7-7 duty cycle distortion d cd 35 50 65 % note 7-8 overshoot and undershoot v os --5% jitter 1.4 ns note 7-9 table 7-13: 10base-t transceiver characteristics parameter symbol min. typ. max. unit note transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 7-10 receiver differential squelch threshold v ds 300 420 585 mv table 7-11: i/o buffer characteristics (continued) parameter symbol min. typ. max. unit note downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 201 lan9730/lan9730i 7.5 ac specifications this section details the various ac timing specifications of the device. 7.5.1 equivalent test load output timing specifications assume the 25 pf equivalent test load illustrated in figure 7-1 below, unless otherwise specified. note: the hsic_data and hsic_strobe pin timing adheres to the hsic 1.0 specification. refer to the high- speed interchip usb electrical specification revisi on 1.0 (09-23-07) and usb hsic ecn for detailed usb timing information. note: the ethernet tx/rx pin timing adheres to the i eee 802.3 specification. refer to the ieee 802.3 specifica- tion for detailed ethernet timing information. figure 7-1: output eq uivalent test load 25 pf output downloaded from: http:///
lan9730/lan9730i ds00001946a-page 202 ? 2012-2015 microchip technology inc. 7.5.2 power sequence timing power supplies must adhere to the following rules: all power supplies of the same voltage must be powered up/down together. there is no power-up sequencing requirement, however all power supplies must reach operational levels within the time periods specified in table 7-14 . there is no power-down sequencing or timing requir ement, however the device must not be powered for an extended period of time without all supplies at operational levels. do not drive input signals without power supplied to the device. it is acceptable for the 3.3 v supplies to remain powered up while the 1.2 v supplies are at zero volts for a period not to exceed 750 ms. in this case, nreset must be asserted while 1.2 v is off, and must remain asserted for a minimum of 50 ms after the 1.2 v supplies reach operational level. configuration straps must meet the require- ments specified in section 7.5.4, "reset and configuration strap timing," on page 203 . note: when operating with an external 1.2 v power source, t he 1.2 v input must not exceed the 3.3 v source by more than 0.4 v. note: violation of these specifications may damage the device. note: a power-on reset (por) occurs whenever power is initially applied to the device, or if power is removed and reapplied to the device. a timer within the device will assert the internal reset for approximately 22 ms. figure 7-2: power sequence timing table 7-14: power sequence timing values symbol description min. typ. max. unit t pon power supply turn on time 0 750 ms all 3.3 v power supply pins all 1.2 v power supply pins t pon downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 203 lan9730/lan9730i 7.5.3 power-on configuration strap valid timing figure 7-3 illustrates the configuration strap valid timing requirement in relation to power-on. in order for valid configu- ration strap values to be read at power-on, the following timing requirements must be met. 7.5.4 reset and configuration strap timing figure 7-4 illustrates the nreset pin timing r equirements and its relati on to the configuration strap pins and output drive. assertion of nreset is not a requi rement. however, if used, it must be asserted for the minimum period specified. figure 7-3: power-on config uration strap valid timing table 7-15: power-on configuration strap valid timing symbol description min. typ. max. unit t cfg configuration strap valid time 15 ms figure 7-4: nreset reset pin timing table 7-16: nreset reset pin timing values symbol description min. typ. max. unit t rstia nreset input assertion time 1 s t css configuration strap pins setu p to nreset deassertion 200 ns t csh configuration strap pins hold after nreset deassertion 10 ns t odad output drive after nr eset deassertion 30 ns vdd33io configuration straps t cfg 2.0 v t css nreset configuration strap pins t rstia t csh output drive t odad downloaded from: http:///
lan9730/lan9730i ds00001946a-page 204 ? 2012-2015 microchip technology inc. 7.5.5 eeprom timing the following specifies the eeprom ti ming requirements for the device: figure 7-5: eeprom timing table 7-17: eeprom timing values symbol description min typ max unit t ckcyc eeclk cycle time 1110 1130 ns t ckh eeclk high time 550 570 ns t ckl eeclk low time 550 570 ns t cshckh eecs high before rising edge of eeclk 1070 ns t cklcsl eeclk falling edge to eecs low 30 ns t dvckh eedo valid before rising edge of eeclk 550 ns t ckhinvld eedo invalid after rising edge eeclk 550 ns t dsckh eedi setup to rising edge of eeclk 90 ns t dhckh eedi hold after rising edge of eeclk 0 ns t cshdv eedio valid after eecs high (verify) 600 ns t dhcsl eedio hold after eecs low (verify) 0 ns t csl eecs low 1070 ns eeclk eedo eedi eecs t cshckh eedi (verify) t ckh t ckl t ckcyc t cklcsl t csl t dvckh t ckhinvld t dsckh t dhckh t dhcsl t cshdv downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 205 lan9730/lan9730i 7.5.6 mii interface timing this section specifies the mii interface transmit and receive timing. note 7-11 timing was designed for a system load between 10 pf and 25 pf. note: the mii timing adheres to the ieee 802.3 specification. refer to the ieee 802.3 specification for additional mii timing information. figure 7-6: mii transmit timing table 7-18: mii transmit timing values symbol description min max units notes t clkp txclk period 40 ns t clkh txclk high time t clkp *0.4 t clkp *0.6 ns t clkl txclk low time t clkp *0.4 t clkp *0.6 ns t val txd[3:0], txen, txer output valid from rising edge of txclk 22.0 ns note 7-11 t invld txd[3:0], txen, txer output invalid from ris- ing edge of txclk 0n s note 7-11 txclk (input) txd[3:0] (output) txen, txer (output) t clkh t clkl t clkp t val t invld t val t val t invld downloaded from: http:///
lan9730/lan9730i ds00001946a-page 206 ? 2012-2015 microchip technology inc. note 7-12 timing was designed for a system load between 10 pf and 25 pf. figure 7-7: mii receive timing table 7-19: mii receive timing values symbol description min max units notes t clkp rxclk period 40 ns t clkh rxclk high time t clkp *0.4 t clkp *0.6 ns t clkl rxclk low time t clkp *0.4 t clkp *0.6 ns t su rxd[3:0], rxdv setup time to rising edge of rxclk 8.0 ns note 7-12 t hold rxd[3:0], rxdv hold time after rising edge of rxclk 9.0 ns note 7-12 rxclk (input) t su rxd[3:0] (input) rxdv, rxer (input) t clkh t clkl t clkp t hold t su t hold t hold t su t hold downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 207 lan9730/lan9730i 7.5.7 turbo mii interface timing this section specifies the turbo mii interface transmit and receive timing. note 7-13 timing was designed for a system load between 10 pf and 15 pf. figure 7-8: turbo mii transmit timing table 7-20: turbo mii transmit timing values symbol description min max units notes t clkp txclk period 20 ns t clkh txclk high time t clkp *0.4 t clkp *0.6 ns t clkl txclk low time t clkp *0.4 t clkp *0.6 ns t val txd[3:0], txen, txer output valid from rising edge of txclk 12.5 ns note 7-13 t invld txd[3:0], txen, txer output invalid from rising edge of txclk 1.5 ns note 7-13 txclk (input) txd[3:0] (output) txen, txer (output) t clkh t clkl t clkp t val t invld t val t val t invld downloaded from: http:///
lan9730/lan9730i ds00001946a-page 208 ? 2012-2015 microchip technology inc. note 7-14 timing was designed for a system load between 10 pf and 15 pf. figure 7-9: turbo mii receive timing table 7-21: turbo mii receive timing values symbol description min max units notes t clkp rxclk period 20 ns t clkh rxclk high time t clkp *0.4 t clkp *0.6 ns t clkl rxclk low time t clkp *0.4 t clkp *0.6 ns t su rxd[3:0], rxdv setup time to rising edge of rxclk 5.5 ns note 7-14 t hold rxd[3:0], rxdv hold time after rising edge of rxclk 0n s note 7-14 rxclk (input) t su rxd[3:0] (input) rxdv, rxer (input) t clkh t clkl t clkp t hold t su t hold t hold t su t hold downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 209 lan9730/lan9730i 7.5.8 jtag timing this section specifies the jtag timing of the device. figure 7-10: jtag timing table 7-22: jtag timing values symbol description min max units notes t tckp tck clock period 66.67 ns t tckhl tck clock high/low time t tckp *0.4 t tckp *0.6 ns t su tdi, tms setup to tck rising edge 10 ns t h tdi, tms hold from tck rising edge 10 ns t dov tdo output valid from tck falling edge 16 ns t doinvld tdo output invalid from tck falling edge 0 ns tck (input) tdi, tms (inputs) t tckhl t tckp t tckhl t su t h t dov tdo (output) t doinvld downloaded from: http:///
lan9730/lan9730i ds00001946a-page 210 ? 2012-2015 microchip technology inc. 7.6 clock circuit the device can accept either a 25 mhz crystal (preferred) or a 25 mhz single-ended clock oscillator (+/-50ppm) input. if the single-ended clock oscillator method is implemented, xo should be left un connected and xi should be driven with a nominal 0-3.3 v clock signal. the input clock duty cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (xi/xo). either a 300 w or 100 w 25 mhz crystal may be utilized. the 300 w 25 mhz crystal specifications are detailed in section 7.6.1 . the 100 w 25 mhz crystal specifications are detailed in section 7.6.2 . 7.6.1 300 w 25 mhz cr ystal specifications when utilizing a 300 w 25 mhz crystal, the following circuit design ( figure 7-11 ) and specifications ( table 7-23 ) are required to ensure proper operation. figure 7-11: 300 w 25 mhz crystal circuit table 7-23: 300 w crystal specifications parameter symbol min. nom. max. unit note crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - +/-50 ppm note 7-15 frequency stability over temp f temp - - +/-50 ppm note 7-15 frequency deviation over time f age - +/-3 to 5 - ppm note 7-16 total allowable ppm budget - - +/-50 ppm note 7-17 shunt capacitance c o - 7 typ - pf load capacitance c l - 20 typ - pf drive level p w 300 - - w equivalent series resistance r 1 - - 50 ohm operating temperature range note 7-18 - note 7-19 o c xi pin capacitance - 3 typ - pf note 7-20 xo pin capacitance - 3 typ - pf note 7-20 lan9730 xo xi y1 c 1 c 2 downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 211 lan9730/lan9730i 7.6.2 100 w 25 mhz cr ystal specifications when utilizing a 100 w 25 mhz crystal, the following circuit design ( figure 7-12 ) and specifications ( table 7-24 ) are required to ensure proper operation. note 7-15 the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any partic ular application must meet the i eee +/-50 ppm total ppm budget, the combination of these two values must be approximately +/-45 ppm (allowing for aging). note 7-16 frequency deviation over time is also referred to as aging. note 7-17 the total deviation for the transm itter clock frequency is specif ied by ieee 802.3u as +/-50 ppm. note 7-18 0 o c for commercial version, -40 o c for industrial version. note 7-19 +70 o c for commercial version, +85 o c for industrial version. note 7-20 this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xo/xi pin and pcb capacitance valu es are required to accurately calculate the value of the two external load capacitors. these two external load capacitors determine the accuracy of the 25.000 mhz frequency. figure 7-12: 100 w 25 mhz crystal circuit table 7-24: 100 w crystal specifications parameter symbol min. nom. max. unit note crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - +/-50 ppm note 7-15 frequency stability over temp f temp - - +/-50 ppm note 7-15 frequency deviation over time f age - +/-3 to 5 - ppm note 7-16 total allowable ppm budget - - +/-50 ppm note 7-17 shunt capacitance c o --5p f load capacitance c l 8 - 12 pf drive level p w - 100 w equivalent series resistance r 1 - - 80 ohm xo series resistor r s 495 500 505 ohm operating temperature range note 7-18 - note 7-19 o c xi pin capacitance - 3 typ - pf note 7-20 xo pin capacitance - 3 typ - pf note 7-20 lan9730 xo xi r s y1 c 1 c 2 downloaded from: http:///
lan9730/lan9730i ds00001946a-page 212 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 213 lan9730/lan9730i 8.0 packaging information % $ & & & $ % & '$780% '$780$ & 6($7,1* 3/$1( 1 ; 7239,(: 6,'(9,(: %277209,(: 127( 1 & $ % & $ % & & 0lfurfkls7hfkqrorj\'udzlqj&$6khhwri ; ; )ruwkhprvwfxuuhqwsdfndjhgudzlqjvsohdvhvhhwkh0lfurfkls 3dfndjlqj6shflilfdwlrqorfdwhgdw kwwszzzplfurfklsfrpsdfndjlqj note: 56l very thin quad flat, no lead package (rt) - 8x8 mm body [vqfn] with 5.9x5.9 mm ex posed pad; punch singulated ' ( ' ( 127( h h ;e / ' ( . $ $ $ downloaded from: http:///
lan9730/lan9730i ds00001946a-page 214 ? 2012-2015 microchip technology inc. microchip technology drawing c04-375a sheet 2 of 2 number of terminals overall height terminal width terminal length mold cap thickness pitch standoff units dimension limits a1 a b a2 e l n 0.50 bsc 0.30 0.18 0.70 0.00 0.230.40 0.850.02 millimeters min nom 56 0.50 0.30 1.000.05 max k- 0.20 - ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1.2. 3. noes: pin 1 visual index feature may vary, but must be located within the hatched area. package is punch singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: overall width overall length exposed pad width exposed pad length d e2 d2 e 5.80 8.00 bsc 5.90 8.00 bsc 6.00 d1 e1 molded top width molded top length 7.65 7.65 7.75 7.75 7.85 7.85 - - 0.90 5.80 5.90 6.00 56l very thin quad flat, no lead package (rt) - 8x8 mm body [vqfn] with 5.9x5.9 mm ex posed pad; punch singulated downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 215 lan9730/lan9730i recommended land pattern dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 5.90 5.90 millimeters 0.50 bsc min e max 7.90 contact pad length (x56) contact pad width (x56) y1 x1 0.69 0.28 microchip technology drawing c04-2375a nom silk screen 12 20 c1 contact pad spacing 7.90 contact pad to center pad (x52) g1 0.20 thermal via diameter v thermal via pitch ev 0.331.20 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 1.2. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: e ev ev c2 c1 x2 y2 ?v y1 g1 x1 56l very thin quad flat, no lead package (rt) - 8x8 mm body [vqfn] with 5.9x5.9 mm ex posed pad; punch singulated downloaded from: http:///
lan9730/lan9730i ds00001946a-page 216 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 217 lan9730/lan9730i appendix a: revision history revision level and date section/figure/ entry correction rev. a (07-24-15) all microchip branding. changed qfn to vqfn rev. a replaces previous numbered datasheet releases. section 7.2 updated 1.2 v supply voltage operating conditions to 1.2 v +10%/-5% section 7.4, "dc specifications" , table 7-11 changed: v ili min from -0.3 to (iclk buffer) v ihi min from 0.33 - 0.35 to 0.8 (iclk buffer) v ihi max from 3.3 to (iclk buffer) i ih min from -4.75 to -10 (hsic buffer) i ih max from 4.75 to 10 (hsic buffer) section 7.6, "clock circuit" added new 100 w crystal specifications and circuit diagram. the sec- tion is now split into two subsections, one for 300 w crystals and the other for 100 w crystals. chapter 8, "packag- ing information" updated package information product identifica- tion system added rev. 1.0 (06-18-12) all initial release downloaded from: http:///
lan9730/lan9730i ds00001946a-page 218 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 219 lan9730/lan9730i the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep customer s current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
lan9730/lan9730i ds00001946a-page 220 ? 2012-2015 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: lan9730, lan9730i temperature range: blank = 0 ? c to +70 ? c (commercial) i = -40 ? c to +85 ? c (automotive, industrial) package: abzj = vqfn (56-pin) tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) examples: a) LAN9730-ABZJ 0 ? c to +70 ? c, 56-pin vqfn, tray b) lan9730i-abzj-tr -40 ? c to +85 ? c, 56-pin vqfn, tape & reel note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sale s office for package availability with the tape and reel option. reel size is 3,000. part no. device [x] temperature range xxxx package [xx] (1) tape and reel option downloaded from: http:///
? 2012-2015 microchip technology inc. ds00001946a-page 221 information contained in this publication regarding device applications and the like is provided on ly for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashf lex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code gener ation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2015, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 978-1-63277-410-1 note the following details of the code protection f eature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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